UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 31587

MIG Virtex-5 FPGA QDRII - Update Design output for an x36 design requires updates to output UCF and top-level RTL for DCI Cascade

Description

"Update Design" can be used to update a MIG v2.0 Virtex-5 FPGA QDRII x36 design. 

However, because MIG 2.0 designs did not include master bank information, the generated design in MIG v2.3 and later is missing required information. 

Specifically, the output of Update Design in MIG v2.3 and later is missing the required DCI Cascade constraint in the UCF file and the master bank pin logic in the top level RTL. 

This information must be added to the Update Design output for successful implementation of the design. 

If these additions are not made, MAP fails with the following errors: 

ERROR:Place:899 - The following IOBs use the Digitally Controlled Impedance feature (DCI) and have been locked (LOC constraint) to the I/O bank 23. This feature requires the VRN and VRP pins within the same I/O bank to be connected to reference resistors. The following VR pins are currently locked and can't be used to supply the necessary reference. 

IO Standard: Name = HSTL_I_DCI_18, VREF = 0.90, VCCO = 1.80, TERM = SPLIT 

List of locked IOB's: 

qdr_cq_n<0> 

qdr_q<0> 

qdr_q<1> 

qdr_q<2> 

qdr_q<3> 

qdr_q<4> 

qdr_q<5> 

qdr_q<6> 

qdr_q<7> 

qdr_q<8> 

qdr_q<9> 

qdr_q<10> 

qdr_q<11> 

qdr_q<20> 

qdr_q<12> 

qdr_q<21> 

qdr_q<13> 

qdr_q<30> 

qdr_q<22> 

qdr_q<14> 

qdr_q<31> 

qdr_q<23> 

qdr_q<15> 

qdr_q<32> 

qdr_q<24> 

qdr_q<16> 

qdr_q<33> 

qdr_q<25> 

qdr_q<17> 

qdr_q<34> 

qdr_q<26> 

qdr_q<18> 

qdr_q<35> 

qdr_q<27> 

qdr_q<19> 

qdr_q<28> 

qdr_q<29> 

qdr_cq<0> 

 

List of occupied VR Sites: 

VR site IOB_X0Y375 is occupied by comp qdr_q<21> 

VR site IOB_X0Y374 is occupied by comp qdr_q<22> 

ERROR:Pack:1654 - The timing-driven packing phase encountered an error."

Solution

Updates Required for Top-level RTL: 

Verilog 

1. Add MASTERBANK_PIN_WIDTH parameter to the top parameter list: 

parameter MASTERBANK_PIN_WIDTH = 1,  

 

2. Add masterbank_sel_pin to the port declaration list: 

/*synthesis syn_keep = 1 */(* S = "TRUE" *) 
input [MASTERBANK_PIN_WIDTH-1:0] masterbank_sel_pin, 

 

3. Add masterbank_sel_pin to the signal declaration list: 

(* KEEP = "TRUE" *) wire [MASTERBANK_PIN_WIDTH-1:0] masterbank_sel_pin_out/*synthesis syn_keep = 1 */; 

 

4. Add dummy pin logic: 

genvar dpw_i; 
generate 
for(dpw_i = 0; dpw_i < MASTERBANK_PIN_WIDTH; dpw_i=dpw_i+1)begin : DUMMY_INST1 
MUXCY DUMMY_INST2 

.O (masterbank_sel_pin_out[dpw_i]), 
.CI (masterbank_sel_pin[dpw_i]), 
.DI (1'b0), 
.S (1'b1) 
) /*synthesis syn_noprune = 1 */; 
end 
endgenerate 

 

VHDL 

1. Add MASTERBANK_PIN_WIDTH parameter to the top parameter list: 

MASTERBANK_PIN_WIDTH : integer := 1;  

 

2. Add masterbank_sel_pin to the port declaration list: 

masterbank_sel_pin : in std_logic_vector((MASTERBANK_PIN_WIDTH-1) downto 0); 

 

3. Add masterbank_sel_pin to the signal declaration list: 

signal masterbank_sel_pin_out : std_logic_vector((MASTERBANK_PIN_WIDTH-1) downto 0); 

 

4. Add the following attribute declaration: 

attribute syn_useioff : boolean; 

attribute IOB : string; 

attribute keep : string; 

attribute S : string; 

attribute syn_noprune : boolean; 

attribute syn_keep : boolean; 

 

attribute keep of masterbank_sel_pin_out : signal is "true"; 

attribute S of masterbank_sel_pin : signal is "TRUE"; 

attribute syn_keep of masterbank_sel_pin_out : signal is true; 

attribute syn_keep of masterbank_sel_pin : signal is true; 

 

5. Add dummy pin logic: 

DUMMY_INST1 : for dpw_i in 0 to MASTERBANK_PIN_WIDTH-1 generate 

attribute syn_noprune of DUMMY_INST : label is true; 

begin 

DUMMY_INST : MUXCY 

port map ( 

O => masterbank_sel_pin_out(dpw_i), 

CI => masterbank_sel_pin(dpw_i), 

DI => '0', 

S =>'1' 

); 

end generate; 

 

Updates Required for UCF: 

1. Add the DCI Cascade constraint with the appropriate Master and Slave banks (data read banks) information.

Information on adding this constraint with the correct syntax is detailed in the MIG output UCF. 

 

2. Add the following constraints for the masterbank_sel_pin: 

NET "masterbank_sel_pin[*]" IOSTANDARD = HSTL_I_DCI_18; 
NET "masterbank_sel_pin[*]" S; 

 

3. Allocate a pin for the masterbank_sel_pin in the selected master bank: 

NET "masterbank_sel_pin[0]" LOC = "xxx" ; #Bank xx 

 

Note: If there is more than one master bank for the updated design, the MASTERBANK_PIN_WIDTH parameter value will be equal to the number of master banks. 

The UCF must have LOC constraints for all of the masterbank_sel_pin pins.

AR# 31587
Date Created 09/08/2008
Last Updated 12/01/2014
Status Active
Type General Article
Devices
  • Virtex-5 FXT
  • Virtex-5 LX
  • Virtex-5 LXT
  • More
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Less
IP
  • MIG