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AR# 31603

10.1 Virtex-5 MAP - "INTERNAL_ERROR:Pack:pktbaplacepacker.c:897:1.139.4.6 - Unable to obey placement request which requires the combination ..."

Description

My design fails with the following internal error. What does the error mean, and how can I avoid it?

NOTE: Multiple variations of this error have been identified in the past. Make note of the specific circumstances identified and the software revisions involved when determining whether this Answer Record applies to your error.

"Physical synthesis completed.

INTERNAL_ERROR:Pack:pktbaplacepacker.c:897:1.139.4.6 - Unable to obey placement request which requires the combination

of the following comp blocks into the SLICE_X111Y83 site. comp:

U_DSPIF.U_MASTER_BLOCK.S_END_IO_M_WR_WRITEDATA_1_sqmuxa_REPLICA_11 comp:

U_DSPIF.U_MASTER_BLOCK.S_END_IO_M_WR_WRITEDATA_1_sqmuxa comp: U_MONITOR/N_1623 comp:

CHANNEL_ENCODER_I/TrChEncoder_i/ProcInDataW(19) comp: CHANNEL_ENCODER_I/TrChEncoder_i/ProcInDataW(17) comp:

CHANNEL_ENCODER_I/TrChEncoder_i/ProcInDataW(25) comp: CHANNEL_ENCODER_I/TrChEncoder_i/ProcInDataW(15) The

fragment blocks involved are as follows: LUT symbol

"U_DSPIF.U_MASTER_BLOCK.S_END_IO_M_WR_WRITEDATA_1_sqmuxa_REPLICA_11" (Output Signal =

U_DSPIF.U_MASTER_BLOCK.S_END_IO_M_WR_WRITEDATA_1_sqmuxa_REPLICA_11) LUT symbol

"U_DSPIF/U_MASTER_BLOCK/S_END_IO_M_WR_WRITEDATA_1_sqmuxa" (Output Signal =

U_DSPIF.U_MASTER_BLOCK.S_END_IO_M_WR_WRITEDATA_1_sqmuxa) LUT symbol

"U_DSPIF/U_MASTER_BLOCK/S_END_IO_M_WR_WRITEDATA_2_sqmuxa" (Output Signal =

U_DSPIF.U_MASTER_BLOCK.S_END_IO_M_WR_WRITEDATA_2_sqmuxa) LUT symbol

"U_DSPIF/U_MASTER_BLOCK/END_IO_M_WR_WRITEDATA_iv[13]" (Output Signal = U_DSPIF.U_MASTER_BLOCK.N_14120_i) LUT symbol

"U_MONITOR/MON_OUT_18_0_0_1[13]" (Output Signal = U_MONITOR/N_1623) FLOP symbol

"CHANNEL_ENCODER_I/TrChEncoder_i/Reg/ProcInDataReg[19]" (Output Signal =

CHANNEL_ENCODER_I/TrChEncoder_i/ProcInDataW(19)) FLOP symbol "CHANNEL_ENCODER_I/TrChEncoder_i/Reg/ProcInDataReg[17]"

(Output Signal = CHANNEL_ENCODER_I/TrChEncoder_i/ProcInDataW(17)) FLOP symbol

"CHANNEL_ENCODER_I/TrChEncoder_i/Reg/ProcInDataReg[25]" (Output Signal =

CHANNEL_ENCODER_I/TrChEncoder_i/ProcInDataW(25)) FLOP symbol "CHANNEL_ENCODER_I/TrChEncoder_i/Reg/ProcInDataReg[15]"

(Output Signal = CHANNEL_ENCODER_I/TrChEncoder_i/ProcInDataW(15)) Function generators

U_DSPIF.U_MASTER_BLOCK.S_END_IO_M_WR_WRITEDATA_1_sqmuxa_REPLICA_11 and

U_DSPIF/U_MASTER_BLOCK/S_END_IO_M_WR_WRITEDATA_1_sqmuxa are not compatible. The two function generators can not share

a LUT site.

Final packing quit early."

Solution

This error is an indication that the placer incorrectly chose BEL locations with a component (usually a Slice) that the packer was later unable to successfully configure into a Slice component. The software fault can be due to the placer incorrectly validating a bad placement selection, or due to the packer incorrectly rejecting a valid placement. It is possible to avoid the error by using packing constraints to force a valid component construct.

This problem has been fixed in the latest 10.1 Service Pack available at:

http://www.xilinx.com/support/download/

The first service pack containing the fix is 10.1 Service Pack 3.

NOTE: This error can be the result of different problems. While all known causes of this error are fixed for ISE 10.1sp3, it is possible that similar errors will occur in 10.1sp3 and future revisions. The problem should be considered to be new and reported to Xilinx via a WebCase:

http://www.xilinx.com/support/clearexpress/websupport.htm

AR# 31603
Date Created 09/03/2008
Last Updated 12/15/2012
Status Active
Type General Article