UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 31615

10.1 EDK SP3, xps_ll_temac_v1_01_b - What constraints do I need for a Virtex-II Pro design?

Description

What constraints do I need for a Virtex-II Pro design?

Solution

The following constraints are required for a Virtex-II Pro design in EDK 10.1sp3, and they have to be appended to the top-level UCF file.

############################################################

# Reset path constraints #

# These constraints add a measure of protection against #

# metastability and skew in the reset nets. #

############################################################

NET "*/I_TRIMAC_INST/I_TRIMAC_INST/RXRSTGENNOEN.I_SYNC_RX_RESET_I/RESET_OUT" MAXDELAY = 6100 ps;

NET "*/I_TRIMAC_INST/I_TRIMAC_INST/TXRSTGENNOEN.I_SYNC_TX_RESET_I/RESET_OUT" MAXDELAY = 6100 ps;

NET "*/I_TRIMAC_INST/I_TRIMAC_INST/INT_GMII_MII_RX_RST" MAXDELAY = 6100 ps;

NET "*/I_TRIMAC_INST/I_TRIMAC_INST/I_SYNC_GMII_MII_TX_RESET_I/RESET_OUT" MAXDELAY = 6100 ps;

NET "*/I_TRIMAC_INST/I_TRIMAC_INST/G_SYNC_MGMT_RESET.I_SYNC_MGMT_RESET_HOST_I/RESET_OUT" MAXDELAY = 6100 ps;

############################################################

# RX Clock period Constraints #

############################################################

NET "*rx_gmii_mii_clk_int*" TNM_NET = "clk_rx_int";

TIMEGRP "rx_clock" = "clk_rx_int";

NET "*gmii_rx_clk*" TNM_NET = "clk_rx_core";

TIMEGRP "rx_clock_core" = "clk_rx_core";

TIMESPEC "TS_rx_clk_core" = PERIOD "rx_clock_core" 7990 ps HIGH 50 %;

############################################################

# TX Clock period Constraints #

############################################################

NET "*tx_gmii_mii_clk*" TNM_NET = "clk_tx_gmii";

TIMEGRP "tx_clock_gmii" = "clk_tx_gmii";

TIMESPEC "TS_tx_clk_gmii" = PERIOD "tx_clock_gmii" 8000 ps HIGH 50 %;

NET "*mii_tx_clk*" TNM_NET = "clk_tx_core";

TIMEGRP "tx_clock_core" = "clk_tx_core";

TIMESPEC "TS_tx_clk_core" = PERIOD "tx_clock_core" 7990 ps HIGH 50 %;

############################################################

# Crossing of Clock Domain Constraints: please do not edit #

############################################################

# Flow Control logic reclocking

INST "*I_TRIMAC_INST/I_FLOW/I_RX_PAUSE/GOOD_FRAME_TO_TX" TNM="flow_rx_to_tx";

INST "*I_TRIMAC_INST/I_FLOW/I_RX_PAUSE/PAUSE_REQ_TO_TX" TNM="flow_rx_to_tx";

INST "*I_TRIMAC_INST/I_FLOW/I_RX_PAUSE/PAUSE_VALUE_TO_TX*" TNM="flow_rx_to_tx";

TIMESPEC "TS_flow_rx_to_tx" = FROM "flow_rx_to_tx" TO "tx_clock_core" 8000 ps DATAPATHONLY;

# Configuration Register reclocking

INST "*I_TRIMAC_INST/MANIFGEN.I_MANAGEN/I_CONF/RX0_OUT*" TNM="config_to_rx";

INST "*I_TRIMAC_INST/MANIFGEN.I_MANAGEN/I_CONF/RX1_OUT*" TNM="config_to_rx";

INST "*I_TRIMAC_INST/MANIFGEN.I_MANAGEN/I_CONF/FC_OUT_29" TNM="config_to_rx";

TIMESPEC "TS_config_to_rx" = FROM "config_to_rx" TO "rx_clock_core" TIG;

TIMESPEC "TS_rxconfig_to_tx" = FROM "config_to_rx" TO "tx_clock_core" TIG;

INST "*I_TRIMAC_INST/MANIFGEN.I_MANAGEN/I_CONF/TX_OUT*" TNM="config_to_tx";

INST "*I_TRIMAC_INST/MANIFGEN.I_MANAGEN/I_CONF/CNFG_OUT_31" TNM="config_to_tx";

INST "*I_TRIMAC_INST/MANIFGEN.I_MANAGEN/I_CONF/FC_OUT_30" TNM="config_to_tx";

TIMESPEC "TS_config_to_tx" = FROM "config_to_tx" TO "tx_clock_core" TIG;

# speed change config

INST "*I_TRIMAC_INST/MANIFGEN.I_MANAGEN/I_CONF/CNFG_OUT_31" TNM="config_to_gmii";

INST "*I_TRIMAC_INST/MANIFGEN.I_MANAGEN/I_CONF/CNFG_OUT_30" TNM="config_to_gmii";

TIMESPEC "TS_config_to_tx_gmii" = FROM "config_to_gmii" TO "tx_clock_gmii" TIG;

TIMESPEC "TS_config_to_rx_gmii" = FROM "config_to_gmii" TO "rx_clock" TIG;

NET sys_clk_s TNM_NET = sys_clk;

TIMEGRP "sys_clk_grp" = "sys_clk" EXCEPT "mdio_logic";

TIMESPEC "TS_host_clk_to_rx_clk" = FROM "sys_clk_grp" TO "rx_clock" TIG;

TIMESPEC "TS_host_clk_to_tx_clk" = FROM "sys_clk_grp" TO "tx_clock_gmii" TIG;

TIMESPEC "TS_host_clk_to_tx_clk_core" = FROM "sys_clk_grp" TO "tx_clock_core" TIG;

TIMESPEC "TS_host_clk_to_rx_clk_core" = FROM "sys_clk_grp" TO "rx_clock_core" TIG;

# Address filter specific cross clocking

INST "*I_TRIMAC_INST/I_ADDR_FILTER_TOP/dynamic_af_gen.I_DYNAMIC_CONFIG/unicast_addr_*" TNM="addr_config_to_rx";

TIMESPEC "TS_addr_config_to_rx" = FROM "addr_config_to_rx" TO "rx_clock_core" TIG;

############################################################

# MDIO Constraints: please do not edit #

############################################################

# Place the MDIO logic in it's own timing groups

INST "*/I_TRIMAC_INST/I_TRIMAC_INST/MANIFGEN.I_MANAGEN/I_PHY/ENABLE_REG" TNM = "mdc_falling";

INST "*/I_TRIMAC_INST/I_TRIMAC_INST/MANIFGEN.I_MANAGEN/I_PHY/READY_INT" TNM = "mdc_rising";

INST "*/I_TRIMAC_INST/I_TRIMAC_INST/MANIFGEN.I_MANAGEN/I_PHY/STATE_COUNT*" TNM = FFS "mdc_rising";

INST "*/I_TRIMAC_INST/I_TRIMAC_INST/MANIFGEN.I_MANAGEN/I_PHY/MDIO_TRISTATE" TNM = "mdc_falling";

INST "*/I_TRIMAC_INST/I_TRIMAC_INST/MANIFGEN.I_MANAGEN/I_PHY/MDIO_OUT" TNM = "mdc_falling";

TIMEGRP "mdio_logic" = "mdc_rising" "mdc_falling";

TIMESPEC "TS_mdio1" = PERIOD "mdio_logic" 400 ns;

TIMESPEC "TS_mdio2" = FROM "mdc_rising" TO "mdc_falling" 200 ns;

TIMESPEC "TS_mdio3" = FROM "mdio_logic" TO "sys_clk_grp" "TS_sys_clk_pin";

TIMESPEC "TS_mdio4" = FROM "sys_clk_grp" TO "mdio_logic" "TS_sys_clk_pin";

# remove paths between domains in the elastic buffers

INST "*WAG_READSYNC*" TNM = "tx_async_reg";

INST "*INT_CRS" TNM = "tx_async_reg";

INST "*COL_REG1" TNM = "tx_async_reg";

INST "*RAG_WRITESYNC*" TNM = "rx_async_reg";

TIMESPEC "ts_tx_async_regs" = TO "tx_async_reg" TIG;

TIMESPEC "ts_rx_async_regs" = TO "rx_async_reg" TIG;

# Need to TIG between the LocalLink clock and the rx_client and tx_client clocks

NET "*/LlinkTemac0_CLK*" TNM_NET = "LLCLK";

NET "*/RxClientClk_0*" TNM_NET = "clk_client_rx0";

NET "*/TxClientClk_0*" TNM_NET = "clk_client_tx0";

TIMESPEC "TS_LL_CLK_2_RX_CLIENT_CLK" = FROM LLCLK TO clk_client_rx0 7800 ps DATAPATHONLY;

TIMESPEC "TS_LL_CLK_2_TX_CLIENT_CLK" = FROM LLCLK TO clk_client_tx0 7800 ps DATAPATHONLY;

TIMESPEC "TS_RX_CLIENT_CLK_2_LL_CLK" = FROM clk_client_rx0 TO LLCLK 7800 ps DATAPATHONLY;

TIMESPEC "TS_TX_CLIENT_CLK_2_LL_CLK" = FROM clk_client_tx0 TO LLCLK 7800 ps DATAPATHONLY;

# Add from BRAM to ClientClks

TIMESPEC "TS_BRAM_CLK_2_RX_CLIENT_CLK" = FROM sys_clk_grp TO clk_client_rx0 7800 ps DATAPATHONLY;

TIMESPEC "TS_BRAM_CLK_2_TX_CLIENT_CLK" = FROM sys_clk_grp TO clk_client_tx0 7800 ps DATAPATHONLY;

TIMESPEC "TS_RX_CLIENT_CLK_2_BRAM_CLK" = FROM clk_client_rx0 TO sys_clk_grp 7800 ps DATAPATHONLY;

TIMESPEC "TS_TX_CLIENT_CLK_2_BRAM_CLK" = FROM clk_client_tx0 TO sys_clk_grp 7800 ps DATAPATHONLY;

INST "*WR_ENABLE*" TNM = "tx_async_reg";

INST "*REG_TX_EN_IN" TNM = "tx_async_reg";

INST "*REG_TX_ER_IN" TNM = "tx_async_reg";

NET "*/GMII_TX_E*_TO_PHY" TNM_NET=TX_PHY_ENR;

NET "*/REG_TX_E*_IN" TNM_NET=REG_TX_PHY_ENR;

TIMESPEC "TS_TX_ER_2_TX_REG" = FROM "TX_PHY_ENR" TO "REG_TX_PHY_ENR" TIG;

INST "*/I_TRIMAC_INST/I_TRIMAC_INST/MANIFGEN.I_MANAGEN*OP_INT*" TNM = "hosttomdc";

INST "*/I_TRIMAC_INST/I_TRIMAC_INST/MANIFGEN.I_MANAGEN*PHY_AD_INT*" TNM = "hosttomdc";

INST "*/I_TRIMAC_INST/I_TRIMAC_INST/MANIFGEN.I_MANAGEN*REG_AD_INT*" TNM = "hosttomdc";

INST "*/I_TRIMAC_INST/I_TRIMAC_INST/MANIFGEN.I_MANAGEN*WR_DATA_INT*" TNM = "hosttomdc";

TIMESPEC "TS_hosttomdc" = FROM "hosttomdc" TIG;

AR# 31615
Date Created 09/15/2008
Last Updated 12/15/2012
Status Active
Type General Article