Known Issue: v1.9, v1.8, v1.7.1, v1.7, v1.6.1, v1.6, v1.5.2, v1.5.1, v1.5, v1.4, v1.3, v1.2, v1.1
A x8 design with lane reversal occurring is susceptible to the known restriction "Receipt of Back-to-Back ACK DLLPs".
For more information on this known restriction, see UG197 v1.4: "Virtex-5 FPGA Integrated Endpoint Block for PCI Express Designs".
A work-around was introduced in v1.8 of the Block Plus Core to handle this problem. However, the work-around does not account for x8 links that are lane reversed. In a x8 lane reversed link, a TX lock up might occur if ACKs are received on consecutive cycles.
A fix for this is available in the v1.9 Rev 1 patch. See (Xilinx Answer 31572) for access to the patch.
01/07/2009 - Added patch availability information.
10/07/2008 - Initial Release.