Initiator/Target for PCI v3.167 - Release Notes and Known Issues

AR#	32324	Search For Another Answer
Topic	SystemIO
Last Updated	04/05/2012
Status	Active

Description

This Release Note and Known Issues Answer Record is for the LogiCORE IP Initiator/Target for PCI v3.167 released in ISE Design Suite 11.1, and it contains the following information: 

• General Information 
• New Features 
• Bug Fixes 
• Known Issues 

For installation instructions, general CORE Generator software known issues, and design tools requirements, see the IP Release Notes Guide at: 
http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf.

Solution

General Information 

The LogiCORE IP PCI v3.167 supports only Virtex-4, Spartan-3, and older architectures. For Virtex-5 devices, use the v4.8 PCI Core. For more information on this core, refer to (Xilinx Answer 31568).  

For general information regarding timing closure in Virtex-4 devices, see (Xilinx Answer 22921).  

New Features 

• ISE 11.1 tool support 

Resolved Issues 

• None 

Known Issues 

(Xilinx Answer 47089) - Initiator/Target for PCI v3.167 - Fails with Java error in ISE software versions 13.4, 13.3, and 13.2
(Xilinx Answer 32498) - LogiCORE IP Initiator/Target v3.167 for PCI - The v3.167 Core does not show up under default CORE Generator view  
(Xilinx Answer 32499) - LogiCORE IP Initiator/Target v4.8 and v3.167 - Simulation Error:$hold( posedge CLK:18310587 ps, posedge I &&& (in_clk_enable1 == 1):18310595 ps, 50 ps );  

• With newer versions of ModelSim, when running the example simulation it might be necessary to add this option to the vsim command: 
  -voptargs="+acc" 
  vsim -voptargs="+acc" -L unisims_ver -t ps work.TEST_TB glbl 
  
  This argument instructs ModelSim not to optimize internal signals in the simulation model. 

Revision History 

04/05/2012 - Added Answer Record 47089
06/17/2009 - Added MTI note on vsim command
09/19/2008 - Initial Release