We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 33884

11.4 Virtex-6 FPGA Editor - Why do I see both RAMB18E1 and RAMB36E1 sites in FPGA Editor?


In previous architectures, FPGA Editor showed the RAM primitives as 2 BELs within a COMP. When I look in FPGA Editor for Virtex-6 devices, there are both RAMB18E1 and RAMB36E1 sites.

What is the reason for this? Can I use the RAMB36E1 and the two RAMB18E1 sites that are associated with it at the same time?


Modeling the RAM primitives this way gives the Placer the flexibility to place each RAMB18E1 primitive separately based on timing requirements. In previous architectures, the RAM BELs were packed together prior to placement without regard to timing requirements.

The RAMB36E1 and two RAMB18E1 primitives associated with it represent the same physical resource. A RAMB36E1 primitive cannot be used when one or both of the RAMB18E1s are used.

AR# 33884
Date 12/15/2012
Status Active
Type General Article
Page Bookmarked