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AR# 34589

MIG Virtex-6 DDR2/DDR3 - General Board Level Debug


This Answer Record provides information on general board level debug for DDR2/DDR3 design using MIG.The information provided in this Answer Record should be the starting point in any hardware debug of a memory interface design.

NOTE: This Answer Record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.


Following is the recommended flow for debugging a hardware issue involving a memory interface:

For detailed information on Verify Memory Implementation Guidelines, refer to:

Each of these steps is detailed in the Debug Guide provided with The Virtex-6 FPGA Memory Interface Solutions User Guide. Go to the DDR2 and DDR3 SDRAM Memory Interface Solution > Debugging Virtex-6 FPGA DDR2/DDR3 SDRAM Designs > Hardware Debug section.

To open a WebCase, go to:

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Associated Answer Records

AR# 34589
Date Created 05/17/2010
Last Updated 12/15/2012
Status Active
Type General Article
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
  • MIG