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AR# 34859

Virtex-6 FPGA Block RAM Design Advisory - Address Space Overlap

Description

Under certain conditions in which addresses overlap, it is possible that the contents of the Virtex-6 FPGA block RAM can become corrupted. This Answer Record provides additional details to that found on page 15 of the Virtex-6 FPGA Block RAM User Guide (UG363), which also includes other types of conflict avoidance descriptions.

Solution

Issue Description:

Under certain conditions it is possible that the contents of the Virtex-6 FPGA block RAM can become corrupted.

The issue only occurs when using either of the following setups with different clocks clocking CLKA and CLKB of the block RAM:
  • True Dual Port (TDP) mode with WRITE_MODE = READ_FIRST for the RAMB36E1 or RAMB18E1 components
  • Simple Dual Port (SDP) mode for the RAMB36E1 or RAMB18E1 components, including the Error Correction Code (ECC) implementation

When a write operation is performed and a subsequent read operation of the other port is attempted on one of the overlapping addresses, the read operation might fail and the contents of the memory locations being written to can become corrupted. If CLKA and CLKB of the Block RAM are driven by the same clock, no collision will occur and read and write operations will succeed with no memory corruption. Please see the figure and table below for further details on what clocking schemes are affected by this issue, and review the 'Work-around' section for ways to work around the issue.



Figure 1:







Table 1: Address Collision Conditions


RAMB36E1 Primitive

RAMB18E1 Primitive
Address Collision
Occurs when all are true:

- both ports are enabled (ENA and ENB = 1)

- not using the same clock on both ports (CLKA CLKB)

- the phase offset between clocks is between 100 ps and 3 ns (or the next clock edge)

- A14-A8, A5, A0 are same for both ports

Occurs when all are true:

- both ports are enabled (ENA and ENB = 1)

- not using the same clock on both ports (CLKA CLKB)

- the phase offset between clocks is between 100 ps and 3 ns (or the next clock edge)

- A13-A7, A4 are same for both ports


Affected Components:
  • RAMB18E1 or RAMB36E1 with WRITE_MODE set to READ_FIRST on either port
  • RAMB18E1 or RAMB36E1 with RAM_MODE=SDP
  • All UNIMacro components with WRITE mode set to READ_FIRST on either port



Behavior in Software:
  • In ISE 11.4 and later software - a warning is generated in designs with block RAM in READ_FIRST mode (including SDP and ECC modes) and CLKA and CLKB are not tied to the same clock.
  • In ISE 12.1 and later - the result of simulation illustrates the problem to the user. The simulation models have been updated to alert the user about this condition and reflects unknowns where corruption could occur.
  • In ISE 12.2 and later, WRITE_FIRST mode support has been added for the Simple Dual-Port mode Block RAM configuration. See the 'Work-around' section for more details.

Affected IP:

Some versions of IP are affected by the address overlap issue. Please use the latest version of IP available in ISE 12.1 or later in order to avoid this issue.



Work-around:
  • For True Dual Port (TDP) modes, determine if READ_FIRST mode is absolutely necessary. If not, use WRITE_FIRST or NO_CHANGE modes.
  • Perform a full timing simulation under all conditions with the updated simulation model when it becomes available in the 12.1 software. At minimum, post-synthesis simulation should be run in order to identify any potential collisions.
  • Starting in 12.2 ISE software, WRITE_FIRST mode is supported for Simple Dual Port (SDP) Block RAM.
    • For all SDP Block RAM with RDCLK and WRCLK driven by the same clock, use READ_FIRST mode, since no collision will occur in this case. If RDCLK and WRCLK of a SDP Block RAM are driven by different clocks, use WRITE_FIRST mode. In WRITE_FIRST mode, users must design around the conflict avoidance requirement that exists when one port performs a write operation and the other port simultaneously reads from the same location.
    • CoreGenerator IP and XST have been updated to support the WRITE_FIRST mode feature. If using the Block RAM Generator to generate Simple Dual Port configurations of Block RAM, select and generate v4.2 of the core to use WRITE_FIRST mode. FIFO Generator v6.2 automatically uses WRITE_FIRST Simple Dual port Block RAM when necessary.
    • To enable WRITE_FIRST mode for SDP Block RAM, add the following two constraints on all desired Block RAM in the UCF file:
    • INST <BRAM_inst_name> WRITE_MODE_A = WRITE_FIRST;
    • INST <BRAM_inst_name> WRITE_MODE_B = WRITE_FIRST;
AR# 34859
Date Created 03/19/2010
Last Updated 07/29/2010
Status Active
Type Design Advisory
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
Tools
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5