The Memory Controller provides a reordering option that reorders received requests to optimize data throughput and latency. The reordering logic breaks down memory accesses into row commands and columns commands and will activate the proper rank, bank, or row based on the current request. The controller will monitor each request and determine the most efficient order to send the requests to allow for the least number of activates. This optimizes throughput and latency.
The number of commands that be stored and reordered will depend on your configuration and on the commands requested. The 7 Series andVirtex-6 DDR2/DDR3 designs do not have command FIFOs like previous architecture, so the number of commands stored will depend on the number of bank machines. Each bank machine holds a single request and the interface will push back until it is processed and the bank machine is freed. If you send a set of requests that are optimal to the reordering algorithm, you will see little or no push back. There is also a starvation mechanism that depends on what other requests are already pending. Xilinx recommends simulating the workload in question and observing the interface behavior to understand exactly how the design will behave since it depends on your configuration.
Enabling/Disabling Reordering Logic
Reordering is used by default but can be turned off and controlled by configuring the ORDERING parameter to "NORM" or "STRICT". "NORM" enables the reordering algorithm in the memory controller while "STRICT" disables reordering. This option can be set in the MIG tool. For more information on using the ORDERING parameter, please refer tothe 7 Series andVirtex-6 FPGA Memory Interface Solutions User GuidesUG586andUG406.
09/20/12- Updated to include 7 Series