Each DQ signal is a bi-directional data signal between the FPGA and the memory device.An OSERDES is used in the write path while an IODELAY and ISERDES are used in the read path.The read path clock is affected by the DQS phase, but not clocked directly by the DQS strobe, for details see (Xilinx Answer 35113).
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Circuitry to support both the write and read leveling requirements for DDR2 and DDR3 SDRAM exist within the logic for each I/O block, and new features have been added to each of the three elements within each I/O block (ISERDES, OSERDES, and IODELAY). The block diagram for the I/O logic and dedicated routing associated with a bidirectional data (DQ) pin is shown in the DQ I/O Block Diagram (Figure 1-50) of UG406.
(Xilinx Answer 35116)MIG - Virtex-6 - DDR2/DDR3 - ISERDES Mode Usage