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AR# 35119

MIG Virtex-6 DDR2/DDR3 PHY - DQ I/O Structure


Each DQ signal is a bi-directional data signal between the FPGA and the memory device.An OSERDES is used in the write path while an IODELAY and ISERDES are used in the read path.The read path clock is affected by the DQS phase, but not clocked directly by the DQS strobe, for details see (Xilinx Answer 35113).

Note: This Answer Record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.


Circuitry to support both the write and read leveling requirements for DDR2 and DDR3 SDRAM exist within the logic for each I/O block, and new features have been added to each of the three elements within each I/O block (ISERDES, OSERDES, and IODELAY). The block diagram for the I/O logic and dedicated routing associated with a bidirectional data (DQ) pin is shown in the DQ I/O Block Diagram (Figure 1-50) of UG406.

(Xilinx Answer 35116)MIG - Virtex-6 - DDR2/DDR3 - ISERDES Mode Usage

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
35189 MIG Virtex-6 DDR2/DDR3 - PHY - Architecture Design N/A N/A
35116 MIG - Virtex-6 - DDR2/DDR3 - ISERDES Mode Usage N/A N/A
AR# 35119
Date Created 05/21/2010
Last Updated 12/15/2012
Status Active
Type General Article
  • Virtex-6 CXT
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