has input signal < sig_name > which will be trimmed"">
Why do I receive the following MAP error when I target Spartan-6 or Virtex-6 devices?
"ERROR:MapLib:979 - LUT2 symbol < LUT_name > has input signal < sig_name > which will be trimmed"
This is due to a problem in the way the HDL is synthesized that causes a MAP error for all Spartan-6 and some Virtex-6 FPGA designs using the DSP48 Macro in 12.1.
To work around this issue, add a PCIN or CARRYIN instruction to the DSP48_Macro.
In cases where a PCIN is not needed, add aCARRYIN instruction and tie the CARRYIN pinto zero.
For a detailed list of LogiCORE IP DSP48 Macro Release Notes and Known Issues, see (Xilinx Answer 33537).