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AR# 35431

LogiCORE IP DSP48 Macro v2.0 - 12.1 MAP "ERROR:MapLib:979 - LUT2 symbol < LUT_name > has input signal < sig_name > which will be trimmed"

Description

Why do I receive the following MAP error when I target Spartan-6 or Virtex-6 devices?

"ERROR:MapLib:979 - LUT2 symbol < LUT_name > has input signal < sig_name > which will be trimmed"

Solution

This is due to a problem in the way the HDL is synthesized that causes a MAP error for all Spartan-6 and some Virtex-6 FPGA designs using the DSP48 Macro in 12.1.

To work around this issue, add a PCIN or CARRYIN instruction to the DSP48_Macro.

In cases where a PCIN is not needed, add aCARRYIN instruction and tie the CARRYIN pinto zero.

For a detailed list of LogiCORE IP DSP48 Macro Release Notes and Known Issues, see (Xilinx Answer 33537).

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
33537 LogiCORE IP DSP48 Macro - Release Notes and Known Issues N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
33537 LogiCORE IP DSP48 Macro - Release Notes and Known Issues N/A N/A
AR# 35431
Date Created 04/27/2010
Last Updated 12/15/2012
Status Active
Type General Article
Tools
  • ISE Design Suite - 12.1