Description

After adding ChipScope Pro analyzer cores in the design, the following error occurs during MAP process:

"ERROR:Pack:2811 - Directed packing was unable to obey the user designconstraints
(MACRONAME=u_chipscope_ila/U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_CS_GAND.U_CS_GAND_SRL/I_V5.U_CS_GAND_SRL_V5/I_USE_RPM_NE0.U_GAND_SRL_SET/I_USE_RPM_NE0.U_GAND_SRL_SET_MSET, RLOC=X0Y10) which requires the combination of the symbols listed below to be packed into a single SLICEM component.

The directed pack was not possible because: The top reasons for failure were:

-> A legal placement was never found for shift register symbol"u_chipscope_ila/U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_CS_GAND.U_CS_GAND_SRL/I_V5.U_CS_GAND_SRL_V5/I_USE_RPM_NE0.U_GAND_SRL_SET/I_WHOLE_SLICE.G_SLICE_IDX[10].U_GAND_SRL_SLICE/U_SRLA".
......

The symbols involved are:
MuxCY symbol
"u_chipscope_ila/U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_CS_GAND.U_CS_GAND_SRL/I_V5.U_CS_GAND_SRL_V5/I_USE_RPM_NE0.U_GAND_SRL_SET/I_WHOLE_SLICE.G_SLICE_IDX[10].U_GAND_SRL_SLICE/U_MUXA" (Output Signal = u_chipscope_ila/U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_CS_GAND.U_CS_GAND_SRL/I_V5.U_CS_GAND_SRL_V5/I_USE_RPM_NE0.U_GAND_SRL_SET/I_WHOLE_SLICE.G_SLICE_IDX[10].U_GAND_SRL_SLICE/U_MUXA/O)
...... "

Solution

The error indicates that MAP is not able to obey the RPM (RLOC) constraints embedded in the ChipScope Pro ILA netlist. The possible causes of this error are listed below:

• MAP fails to meet the RLOC constraints because of limited resources available and complexity of the ILA core. Try either of the following methods:
  • Uncheck "Use RPM" option when inserting or generating the ChipScope Pro ILA core(s). However, this can introduce timing problems of the ChipScope Pro cores. Therefore, check the timing report and make sure there are no timing errors after PAR (with the ChipScope Pro cores in the design).
  • Reduce the size and complexity of the ChipScope Pro ILA core(s). For example, reducing the bit width of the trigger ports and the number of the trigger ports, use simple trigger condition, etc.
• When "read_cores" option of XST is set to "optimize", XST reads the ILA netlist and optimizes the logic.Some elements associated to RLOC constraints were removed by the optimization, which results in the RLOC constraints failing. XST is performing the right optimization, but "-read_cores optimize" should not be applied to the ChipScope Pro cores. The ChipScope Pro cores are designed in an optimized way and do not need any more optimization.
  • To resolve this issue, put the ChipScope Pro core netlists in a separate directory to prevent XST from reading them for optimization, and specify the location of the ChipScope Pro core netlists in the "Macro Search Path" option of Translate.