Most of the time, this Warning will be given if there are latches inferred:
WARNING:Xst:737 - Found 1-bit latch for signal <signal name>
If this warning is found, analyze the logic that created the latch and make sure that this is what was intended.
If this was not intended, there are several things to check:
- Ensure if-else statements assign the net to a value under all conditions.
- Ensure case statements assign a value all signals in all conditions.
- If you are intending to infer a register, make sure to include a clock in the process or always block.
In some cases, latches have been inferred on control signals (for example, the reset signal) but "WARNING:Xst:737" was not issued.
If you see that latches are inferred in the Synthesis report but there are no warnings to show what signals they are inferred for, you can open the Technology Schematic or Schematic in PlanAhead and check connections of the latches to see where the latches are inferred from the code.
The following are two examples where latches are inferred on reset signals:
- The register reset value does not match with the initial value specified in port/signal declaration.
The solution is to have the reset value the same as the initial value.
- The state signal of the state-machine is using integer type.
The solution is to switch to enumerated values or standard logic (std_logic/std_logic_vector).
For more information on why a latch might be inferred, please see (Xilinx Answer 38931)
for the XST Documentation.