Xilinx generally does not recommend inferring latches in a design. This is especially true if the logic is intended to be combinatorial logic. A latch will break the synchronous path and make it difficult for the Xilinx Timing Engine to analyze the path appropriately.
It is always recommend to look through the HDL Synthesis section of the XST report to see if there is a latch inferred. Below is the Warning that a design will have if there are latches inferred:
WARNING:Xst:737 - Found 1-bit latch for signal <signal name>
Once this warning is found, please analyze the logic that created the latch and make sure that this is what was intended. If this was not intended, there are several things to check:
- Ensure if-else if-else statements assign the net to a value under all conditions.
- Ensure case statement assign a value all signals in all conditions.
- If you are intending to infer a register, make sure to include a clock in the process or always block
For more information on why a latch may be inferred, please see
(Xilinx Answer 38931) for the XST Documentation.