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AR# 39999 Design Advisory for Spartan-6 FPGA - 9K Block RAM Initialization Support

When generating a bitsteam with BitGen, the program issues the following warning:

WARNING:PhysDesignFules:2410 - This design is using one or more 9K Block RAMs (RAMB8BWER). 9K Block RAM initialization data, both user defined and default, may be incorrect and should not be used. For more information, please reference Xilinx Answer 39999.

Block RAM used in the 9K mode (RAMB8BWER) can fail to initialize user-specified data or default values (all zeros) during configuration in all Spartan-6 devices using ISE 13.1 and prior software versions. 

A fix has been implemented for this warning when not using encryption in ISE Design Suite 13.2i or later.

This Answer Record describes the Spartan-6 9K Block RAM Initialization issue as listed in the Spartan-6 Errata (includingEN148):

ISE Design Suite 13.2 and Later:

A fix has been implemented for this issue in BitGen, which will be used by default. 

This fix correctly configures the initial value of all 9K block RAM, whether the value is set by the user or to the default value of zero. 

However, the BitGen fix does not work if encryption is used.

In that case, there are other options that have been added in XST and MAP to assist with a work-around.

The BitGen warning messages are still issued to point the user to these details:

BitGen Fix (Yes by default):
 

  • Overview - The BitGen option -g INIT_9K:setting (where setting can be Yes or No) is added in ISE Design Suite 13.2.
    Yes means use the new bitstream format and No means use the original format, which does not properly initialize 9K block RAM.
     
  • Usage - If there are any 9K block RAM used in a design, the new bitstream is generated (-g INIT_9K:Yes).
    Otherwise, the old bitstream is generated.
     
  • Restrictions - Encryption cannot be used with the new bitstream format.
    If you attempt to use encryption with 9K block RAM, BitGen errors out with a message referring to this Answer Record (Xilinx Answer 39999), and explains that -g INIT_9K:No must be set in order for the bit file to be generated.
     
  • Additional Information - The new bitstream format results in a slightly larger bitstream size (<1%).
    For the new bitstream sizes, refer to the Bitstream Overview section of the Spartan-6 FPGA Configuration User Guide (UG380).
    In addition, the BitGen Warning message (as shown above) is still issued as an informative message to point to this answer record.
    It can be safely ignored.

MAP Switch (off by default):

  • The MAP option: -convert_bram8 is added in ISE Design Suite 13.2.
    When used, it re-targets all 9K block RAM in the design to 18K block RAM if resources are available.
    This switch can be added at the command line.
    If you are running through the GUI, in the Advanced Process Properties, there is a box to enter "Other Map Command Line Options".
    By default, this option is not set.

XST Switch (Yes by default):

  • The XST switch: -infer_ramb8 setting (where setting can be Yes or No) is added in ISE Design Suite 13.2.
    When used (set to No), it blocks the inference of 9K block RAM in XST.
    By default, this is set to Yes, which is unchanged behavior from all previous software versions.
    If set to No, XST does not infer the RAMB8 primitive, but any instantiated RAMB8s remain.
    This switch can be added at the command line.
    If you are running through the GUI, in the Advanced Process Properties, there is a box to enter "Other XST Command Line Options".

ISE 13.1 and Prior Software Versions

Description:

  • Bitstream initialization of the 9K block RAM (RAMB8BWER) is not supported in 9K mode.
  • The default initialization values of the 9K block RAM are not supported. If there is not a user-specified initialization value, the default behavior initializes all program contents to zeros. This is not guaranteed in the 9K block RAM.
  • To determine if your design contains 9K block RAM, or XST inferred 9K block RAM, view the MAP report and search for RAMB8BWER.
  • Other operation of block RAM is unaffected:
    • Normal reading and writing of the 9K block RAM functions properly.
    • Initialization, read, and write operations of the 18K block RAM function properly.

Work-arounds:

  • Use ISE Design Suite 13.2.
  • Use the 18K block RAM if the initial content of the block RAM (user-specified or default values)are used or needed.
    • Instantiate RAMB16BWER, not RAMB8BWER.
  • Write to the 9K block RAM to initialize it after configuration (instead of using bitstream initialization or using the default values).
    • CORE Generator:

      • Do not use Block Memory Generator for 9K mode if the initial content of the block RAM (user-specified or default values)are used or needed.
  • If none of the above options are feasible for a design, contact Xilinx Technical Support for further assistance.

Software Impact:

  • XST infers 9K block RAM based on size. If the inferred RAM fits into the RAMB8BWER, it is used.
    • This behavior is seen in all 12.4 and earlier software versions.
    • To use an 18K block RAM instead,RAMB16BWER must be instantiated.

Affected IPs:

Related Issues:

AR# 39999
Date Created 01/25/2011
Last Updated 09/02/2014
Status Active
Type Design Advisory
Devices
  • Spartan-6 LX
  • Spartan-6 LXT
Tools
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
  • ISE Design Suite - 12.3
  • More
  • ISE Design Suite - 12.4
  • ISE Design Suite - 13
  • ISE Design Suite - 13.1
  • ISE Design Suite - 13.2
  • ISE Design Suite - 13.3
  • Less
IP
  • Block Memory Generator