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AR# 40424

13.1 EDK, AXI_Ethernet - Constraint [system.ucf(85)]: NET "*/rx_client_clk" does not match any design objects

Description

I get the following errors during the implementation of a Virtex-6 FPGA Hard TEMAC GMII system with AVB enabled.

ERROR:ConstraintSystem:58 - Constraint <NET "*/rx_client_clk" TNM_NET =
"phy_clk_rx";> [system.ucf(85)]: NET "*/rx_client_clk" does not match any
design objects.
ERROR:ConstraintSystem:58 - Constraint <NET "*/tx_client_clk" TNM_NET =
"phy_clk_tx";> [system.ucf(120)]: NET "*/tx_client_clk" does not match any
design objects.
ERROR:Xflow - Program ngdbuild returned error code 2. Aborting flow execution...

Solution

Modify the following constraints in the UCF file to resolve the above errors.

1. From:
NET "*/rx_client_clk" TNM_NET = "phy_clk_rx";
TIMEGRP "v6_emac_v1_3_clk_phy_rx" = "phy_clk_rx";
TIMESPEC "TS_v6_emac_v1_3_clk_phy_rx" = PERIOD "v6_emac_v1_3_clk_phy_rx" 7.5 ns HIGH 50 %;

To:
NET "*axi_str_avbrx_aclk*" TNM_NET = "phy_clk_rx";
TIMEGRP "v6_emac_v1_3_clk_phy_rx" = "phy_clk_rx";
TIMESPEC "TS_v6_emac_v1_3_clk_phy_rx" = PERIOD "v6_emac_v1_3_clk_phy_rx" 7.5 ns HIGH 50 %;


2. From:
NET "*/tx_client_clk" TNM_NET = "phy_clk_tx";
TIMEGRP "v6_emac_v1_3_clk_ref_mux" = "phy_clk_tx";
TIMESPEC "TS_v6_emac_v1_3_clk_ref_mux" = PERIOD "v6_emac_v1_3_clk_ref_mux" TS_v6_emac_v1_3_clk_ref_gtx HIGH 50%;

To:
NET "*axi_str_avbtx_aclk*" TNM_NET = "phy_clk_tx";
TIMEGRP "v6_emac_v1_3_clk_ref_mux" = "phy_clk_tx";
TIMESPEC "TS_v6_emac_v1_3_clk_ref_mux" = PERIOD "v6_emac_v1_3_clk_ref_mux" TS_v6_emac_v1_3_clk_ref_gtx HIGH 50%;

Re-run implementation after making the above changes to the UCF file.

AR# 40424
Date Created 02/02/2011
Last Updated 05/19/2012
Status Active
Type Error Message
Devices
  • Virtex-6 LXT
  • Virtex-6 SXT
Tools
  • EDK - 13.1
  • ISE Design Suite - 13.1
IP
  • AXI Ethernet
  • Ethernet AVB