It hasbeen discovered that in Spartan-6 FPGA designs that utilize inputs implemented with split internal termination (UNTUNED_SPLIT_XX, where XX is 25, 50, or 75), no internal termination is enabled in hardware.Common indications that are observed include:
This issue does not impact bi-directional signals, so MIG/Memory interface-based designs are not typically affected.
For software versions prior to and including 13.2, the termination can be enabled by making a signal bi-directional with the 3-state control permanently enabled High (output disabled). NOTE: the Save constraint must be utilized to avoid optimization back into an input.
This issue is currently being investigated by the BitGen team, but a fix date is not yet available.
Because the IN_TERM attribute is IOSTANDARD-independent,this issue can occur with many standards; most commonly this would be expected in SSTL, HSTL, and LVCMOS.
The issue is isolated to BitGen, so throughout the implementation process, the design would indicate that IN_TERM is appropriately enabled.