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AR# 40818 Design Advisory for Spartan-6 SelectIO - INTERM_XX not being appropriately Turned On in BitGen for Spartan-6 FPGA inputs

It hasbeen discovered that in Spartan-6 FPGA designs that utilize inputs implemented with split internal termination (UNTUNED_SPLIT_XX, where XX is 25, 50, or 75), no internal termination is enabled in hardware.Common indications that are observed include:

  • unexpected reflections/poor signal integrity
  • lower than expected power consumption
  • lack of a bias on a signal

This issue does not impact bi-directional signals, so MIG/Memory interface-based designs are not typically affected.

For software versions prior to and including 13.2, the termination can be enabled by making a signal bi-directional with the 3-state control permanently enabled High (output disabled). NOTE: the Save constraint must be utilized to avoid optimization back into an input.

This issue is currently being investigated by the BitGen team, but a fix date is not yet available.

Additional Notes:

Because the IN_TERM attribute is IOSTANDARD-independent,this issue can occur with many standards; most commonly this would be expected in SSTL, HSTL, and LVCMOS.

The issue is isolated to BitGen, so throughout the implementation process, the design would indicate that IN_TERM is appropriately enabled.

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
34856 Design Advisory Master Answer Record for Spartan-6 FPGA N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
40000 Spartan-6 - 13.4 Known Issues Related to Spartan-6 FPGA N/A N/A
AR# 40818
Date Created 02/23/2011
Last Updated 05/20/2012
Status Active
Type Design Advisory
Devices
  • Spartan-6 LX
  • Spartan-6 LXT