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AR# 41130

SPI-4.2 - Updated Source Core MMCM settings for using Global Clocking at 1G on Virtex-6 devices

Description

When global clocking is used for the SPI-4.2 Source Core, there are several Virtex-6 MMCM specifications and errata items that restrict the MMCM attribute settings and core performance:
 
  • Fclkin/DIVCLK > 135MHz for BANDWIDTH = HIGH, see (Xilinx Answer 38132) The BANDWIDTH needs to be high for the Source core sysclk to reduce jitter.
  • The Max Fvco value (-1, -1L <1200; -2 <1440; -3 <1600) : UG362 , page 41
  • Cannot use DIVCLK = 3 or 4 when Fclkin > 315MHz, see (Xilinx Answer 38133)
  • Cannot use MULT values of 1,2,3, 4 or fractional values, see (Xilinx Answer 33849)

Solution

The v10.5 and v11.2 cores released in ISE 13.2 will be updated to reflect the below MMCM attributes to ensure that the Bandwidth is set to "HIGH". 

In v10.4 and v11.1 and earlier cores using global clocking at 1G the MMCM attributes will need to be updated as shown below for SysClk in pl4_src_clk.v/vhd. 

For slower rates, the MMCM attributes are already set such that the bandwidth will be set "HIGH" and do not need to be updated.

 

Supported Source Core Performance and Clocking Schemes

 

 Speed Grade
 <=900Mbps  1Gbps  1.1Gbps  1.25Gbps  1.4Gbps
 -1L  Regional/Global
 NA  NA  NA  NA
 -1  Regional/Global
 Regional only
 Regional only
 NA  NA
 -2  Regional/Global
 Regional only
 Regional only
 Regional only
 NA
 -3  Regional/Global
 Regional/Global
 Regional only
 Regional only
 Regional only

 

 MMCM Configuration and Attributes based on Performance and Speed Grade for the Source Core

 

Performance
 Bandwidth  DIVCLK_DIVIDE  CLKFBOUT_MULT_F CLKOUT0_DIVIDE_F
 CLKOUT1_DIVIDE

Up-to 1 Gbps

(MMCM values same

for all speeds)

 HIGH  2  5  2.5  5

 

For a specific frequency and speed grade it might be possible to generate more optimal MMCM settings then the default provided with the core.  

It is recommended to use the latest LogiCORE Clocking Wizard IP to generate the optimum MMCM instantiation for your specific data rate; see (Xilinx Answer 39432) for step-by-step guidance on how to generate an MMCM instantiation for the SPI-4.2 core using the Clocking Wizard IP.

AR# 41130
Date Created 03/14/2011
Last Updated 12/01/2014
Status Active
Type General Article
IP
  • SPI-4 Phase 2 Interface Solutions