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AR# 43243

Design Advisory for Virtex-7 and Kintex-7 FPGA Initial Engineering Samples Integrated Block for PCI Express - Active State Power Management Not Supported for Gen 2 Rates


The Virtex-7 and Kintex-7 GTX in Initial Engineering Sample (ES) Silicon does not support the PCIe Active State Power Management (ASPM) L0s state on the receiver when operating at Gen 2 (5.0 Gb/s) line rate. ASPM is autonomous hardware power management and is described in Chapter 5 of the PCI Express Base Specification. Please refer to the errata document which accompanies the devices to confirm which Initial ES parts are affected.


Systems that Support ASPM Optionality

ASPM L0s state is an optional feature within the PCI Express Base Specification starting with version 2.1 due to the ASPM Optionality Change Notice. The Kintex-7 Integrated Block for PCI Express supports the ASPM Optionality feature, and has the ability to disable ASPM.This is done by setting the Integrated Block attributes:


This can be done by modifying the attributes in the "<core_name>.v[hd]" file found in the generated core's source directory.This file will have the same name as the core entered during the CORE Generator customization process. By default, this file is called pcie_7x_v1_1.v[hd]. Setting these attributes will cause the ASPM Support field in the Link Capability register of the PCI Express Capability structure to 00b and ensures that the system software will not enable ASPM L0s.

Systems that Do Not Support ASPM Optionality

Note that on systems designed prior to version 2.1 of the PCI Express Base Specification, the ability to disable ASPM is not available. Therefore, the Kintex-7 FPGA Integrated Block might behave incorrectly when connected to such a system. In such cases, the PCIe link partner might enter ASPM L0s. For alternative solutions for disabling ASPM on such legacy systems, see (Xilinx Answer 36325).

If ASPM cannot be disabled due to legacy system issues, symptoms that might be exhibited are:

  • Correctable errors
  • Replay timeouts

To verify that the ASPM has been disabled on the link partner, check bits 1:0 of the link partner's Link Control Register. A setting of 00b indicates that ASPM is disabled. For more information on these registers, see Chapter 7 of the PCI Express Base Specification.

NOTE: The issue reported in this answer record has been fixed in productive devices.

Revision History

10/08/2012 - Added note on production devices
05/02/2012 - Updated to clarify which parts are affected
08/19/2011 - Updated title to include Virtex-7, changed ASPM optionality attribute to TRUE
07/28/2011 - Initial release

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
43347 Kintex-7 FPGA Initial Engineering Sample (ES) - Known Issues Master Answer Record N/A N/A
AR# 43243
Date Created 07/27/2011
Last Updated 10/10/2012
Status Active
Type Design Advisory
  • Kintex-7