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AR# 44612

13.2 Timing Analysis - Component Switching Limit Check Is Incorrect for OSERDESE2.CLK


Thexc7vx485t-1 device in ISE Design Suite13.2 reportsthe following Component Switching Limit error regarding theOSERDESE2 CLK pin component.This does not match the data sheet. When will it be fixed?

Component Switching Limit Checks: TS_dac0_dco_P = PERIOD TIMEGRP "dac0_dco_P" 1.627 ns HIGH 50%;
Slack: -0.093ns (period - min period limit)
Period: 1.627ns
Min period limit: 1.720ns (581.395MHz) (Tosper_CLK)
Physical resource: uu1/OSERDESE2_inst1/CLK
Logical resource: uu1/OSERDESE2_inst1/CLK
Location pin: OLOGIC_X1Y302.CLK
Clock network: uu1/dac0_clk614m4

However,in the Virtex-7 FPGAs Data Sheet: DC and Switching Characteristics (DS183),it states that theSDR LVDS transmitter can run upto 625 MHz (-1 part). The 581.395 MHz limit seems incorrect.


This Component Switching Limit check is incorrect in ISE Design Suite13.2. This issue is fixed in ISE Design Suite13.3, where the minimum period/maximum frequency limit of the OSERDESE2.CLK pin (-1 part)is1.452 ns (688.705 MHz).

In ISE Design Suite13.2, you can ignore this Component Switching Limit error as long as the actual frequency does not exceed688.705 MHz.
AR# 44612
Date Created 10/25/2011
Last Updated 12/15/2012
Status Active
Type General Article
  • ISE Design Suite - 13.2