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AR# 47266

Zynq-7000 Example Design - CPU latency to access an AXI Slave using Master AXI GP

Description

This example design allocates 4K of BRAM attached to the M_AXI_GP0 and monitored by ChipScope tool. The softwarethen treats the memory as a "shareable device" or "strongly-ordered," and a ChipScope shot provides the distance between the SEV instruction and the first BVALID signal on the AXI port for LATENCY.

Note: An Example Design is an answer record that providestechnical tips to test a specific functionalityon Zynq-7000. Atip can be a snippet of code, a snapshot, a diagram or a full design implemented with a specific version of the Xilinx tools.It isup to the user to "update" these tips to future Xilinx tools releases and to "modify" the Example Design tofulfill his needs. Limited support is provided by Xilinx on these Example Designs.
Implementation Details
Design Type PS and PL
SW Type Standalone
CPUs Single CPU @ 720MHz
PS Features MMU
PL Cores BRAM, CHIPSCOPE
Boards/Tools ZC702
Xilinx Tools Version EDK 14.1
Other details FCLK @ 150MHz
Address Map
Base Address Size Bus Interface
BRAM 0x41200000 4K S_AXI
Files Provided
zc702_bram_archive.zip
Archived XPS project.
code_latency.c Snippet of code.
Block Diagram

Solution

Step by Step Instructions

1. Import the archived design into XPS and export to SDK.
2. In SDK create a Hello World example.
3. Modify the Hello World example to include the snippet of C code.
4. Program the PL using the BITSTREAM generated by XPS.
5. Setup ChipScope toolto trigger on the EVENTO signal.
6. Run the application.
7. Measure the latency as the time between the rising edge of EVENTO and the BVALID signal on the AXI MASTER Interface.

Expected Results

Strongly-ordered or Shareable device does not change the LATENCY.
Enabling the CACHE (L1 and L2) affects the LATENCY.

Latency

Type

Cache

FCLK cycles

CPU cycles

Time (nS)

Strongly-ordered

Disabled

11

53

74

Strongly-ordered

Enabled

6

29

40

Shareable device

Disabled

11

53

74

Shareable device

Enabled

6

29

40

Attachments

Associated Attachments

Name File Size File Type
zc702_bram_archive.zip 2 MB ZIP
code_latency.c 1 KB C

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
51779 Zynq-7000 AP SoC - Example Designs and Tech Tips N/A N/A
AR# 47266
Date Created 08/07/2012
Last Updated 03/02/2013
Status Active
Type General Article
Devices
  • Zynq-7000
Tools
  • EDK - 14.1
Boards & Kits
  • Zynq-7000 All Programmable SoC ZC702 Evaluation Kit