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AR# 47548

Zynq-7000 AP SoC, APU - Ordering of Read Accesses to the same Memory Location might not be Ensured

Description

The processors operating in an SMP environment can experience a read access bypassed by a following read access to the same memory location. The issue only occurs for read accesses to a memory region that is marked as a Normal Memory Write-Back Shared.

This is not common and there are multiple work-arounds.

Solution

Impact:

Minor. There are multiple work-arounds.

Work-arounds:

The vast majority of multi-processing code is not written in a style which exposes the issue. So the issue is expected to affect very specific areas of code which rely on this read ordering behavior. Refer to the Work-around Details for more information.

Configurations Affected:

Systems that use one or both processors.

Device Revision(s) Affected: All. No plan to fix. Refer to (Xilinx Answer 47916) - Zynq-7000 AP SoC Silicon Revision Differences.

 

The ARM architecture and general rules of coherency require reads to the same memory location to be observed in order. Due to some internal replay path mechanisms, the processor can see a read access bypassed by a following read access to the same memory location, thus not observing the values in program order.

The issue can only occur on a processor working in SMP mode, on memory regions marked as Normal Memory Write-Back Shared.

Work-around Details

  • Use the LDREX instruction instead of standard LDR in volatile memory places where a strict read ordering is required.
  • Insert DMB instruction between the affected LDR which requires this strict ordering rule. This is the recommended work-around for tool chains integration.

Sequence without DMB barrier instructions

Sequence with DMB barrier instructions

The result is that processor 2 can occasionally incorrectly observe Rx == <valueB> and Ry == <valueA>.

The data order is preserved.

 

 

On processor 1

On processor 1

STR <valueA>, [loc]

STR <valueA>, [loc]

 

 

STR <valueB>, [loc]

STR <valueB>, [loc]

 

 

On processor 2

On processor 2

LDR Rx, [loc]

LDR Rx, [loc]

 

DMB

LDR Ry, [loc]

 

 

LDR Ry, [loc]

 

DMB

The problem can affect all forms of memory load instruction except LDREX, LDREXB, LDREXH and LDREXD.

For high-level languages, compilers often optimize away or otherwise re-order multiple accesses to the same memory location, so only memory locations that are declared volatile can be considered to be susceptible to this problem. Furthermore, any barrier operation between the two loads is sufficient to prevent the conditions for triggering the problem, so only lock-free programming methodologies are affected.

Note: The use of LDREX is unpredictable, unless accessing Normal memory, so the second sequence cannot be used as a general workaround for accessing all volatile objects in memory.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
47916 Zynq-7000 AP SoC Devices - Silicon Revision Differences N/A N/A
AR# 47548
Date Created 05/24/2012
Last Updated 06/04/2013
Status Active
Type Design Advisory
Devices
  • Zynq-7000
  • Zynq-7000Q
  • XA Zynq-7000