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AR# 50234

Virtex-6 Integrated PCIe Block Wrapper - Debugging and Packet Analysis Guide

Description

This answer record provides a debugging and packet analysis guide for Virtex-6 FPGA Integrated PCIe Block Wrapper in a downloadable PDF to enhance its usability. Answer Records are Web-based content that are frequently updated as new information becomes available. Visit this answer record to obtain the latest version of the PDF.

Solution

Please download the Virtex-6 Integrated PCIe Block Wrapper - Debugging and Packet Analysis Guide which is attached in PDF format at the end of this answer record; file name is "Xilinx_Answer_50234_V6_PCIe_Debugging_Packet_Signal_Analysis.pdf".

This document describes techniques for debugging issues related to Integrated PCIe Block Wrapper in Virtex-6 FPGA by using ChipScope analyzer. You should have a clear understanding on the flow of packets through different interfaces of your design when debugging PCIe issues. You should be able to identify what type of packets are seen on those interfaces by analyzing the packet header. This document provides a detailed description on tracking packets through different interfaces in the core. Some helpful techniques on how to select signals for triggering in ChipScope analyzer and how to set the correct trigger to capture packets on different interfacesare discussed.

The main objective of this document is to help you debug your design by going into the low level details of the core. This document will help you to debug issues related to both link training and PCIe packet traffic. ChipScope analyzer screenshots are provided to illustrate how to analyze packets and signals.

Attachments

Associated Attachments

AR# 50234
Date Created 08/16/2012
Last Updated 03/02/2013
Status Active
Type General Article
IP
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )