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AR# 51138

14.5 EDK - How can I add interrupts to my AXI CIP generated IP and test this on MicroBlaze or ARM?

Description

The interrupt functionality is missing from the CIP Wizard in EDK.

What should be modified in the generated files to add interrupt support?

Solution

Attached to the end of this answer record is a ZIP file (51138.zip) which can be used as a reference to add interrupt support to a CIP generated AXI IP. The HDL, MPD, and PAO files will need to be updated.

In the user HDL code, a simple counter is implemented to generate an interrupt every 15 seconds (depending on the AXI clock):

  1. Unzip the attached files into a current project directory.
  2. Place the axi_interrupt_v1_00_a file into the pcores folder.
  3. Place the XilinxProcessorIPLib file into the drivers folder (create one if it does not already exist).
  4. Add the axi_interrupt IP to the hardware project in EDK, and tick the C_INTERRUPT_PRESENT box in the Core Configuration in XPS.
  5. For MicroBlaze designs, the application code assumes the system contains an Interrupt controller. In Zynq SoC, simply select the IRQ under the Zynq tab, and add the AXI_Interrupt to the PS interrupt controller.


For testing purposes, there is an example AXI Interrupt Application for both MicroBlaze and Zynq SoC designs. To use this application:

  1. Export to SDK.
  2. Once SDK is open, go to Xilinx Tools -> Repositories and under Local Repositories, point to the drivers folder in the project directory.
  3. Click Rescan Repositories.
  4. Select OK to close the GUI.
  5. To create the BSP, go to File -> New -> Board Support Package.
  6. To create the application, go to File -> New -> Application Project. Name the application, use the existing Board Support Package, then select Next to continue.
  7. Select an Empty Application, then Finish to continue.
  8. Drop down the newly created Application in the Project Explorer view in SDK, and highlight the src folder. Now select File -> New -> Source File. Call it main.c. Select Finish to continue.
  9. In the 51138.zip, there will be a folder called src, there are two files: mb_main.c and zynq_main.c. Depending on your system, copy the contents of the relevant file to your newly created main.c file

 

Note: These applications require at least 128KB of memory.

To see how to port this IP, or other CIP created AXI IP to Vivado IP Integrator, see AR56358

Attachments

Associated Attachments

Name File Size File Type
51138.zip 24 KB ZIP
AR# 51138
Date Created 08/17/2012
Last Updated 06/13/2013
Status Active
Type General Article
Devices
  • Zynq-7000
  • Kintex-7
  • Artix-7
  • More
  • Spartan-6
  • Virtex-6
  • Virtex-7
  • Less
Tools
  • EDK - 14.4
  • EDK - 14.3