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AR# 5126

LogiCORE PCI - Is there enough time to configure the FPGA before PCI reset (RST#) is released (PCI bus configuration timing details)?


General Description:

How much time is allowed for FPGA configuration on a PCI bus?


The v3.0 PCI specification includes a parameter called Tpvrh; defined as the required time between "power good" and the de-assertion of RST#. Tpvrh is 100 ms. This means that the FPGA has 100 ms to configure before RST# is deasserted. It should be possible to configure the FGPA in this time period. Please evaluate configuration options available and select one that configures the part within 100 ms. In many cases, this requires using the select map configuration mode. For more information on configuration options, refer to the device data sheet for your device.

If the PCI core is a 64-bit capable device, then it must be configured by the time RST# is deasserted; otherwise, it might miss the assertion of REQ64#, which indicates a 64-bit PCI bus.

AR# 5126
Date Created 08/21/2007
Last Updated 12/15/2012
Status Active
Type General Article