"> AR# 52049: Artix-7 FPGA General Engineering Sample (GES) - Known Issues Master Answer Record


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AR# 52049

Artix-7 FPGA General Engineering Sample (GES) - Known Issues Master Answer Record


This answer record highlights important requirements and known issues for the Artix-7 FPGA General Engineering Sample (GES) program related to software and IP. Additional silicon limitations might exist, so please reference the 7 Series Errata found on xilinx.com.

This answer record will be updated as new information becomes available regarding known issues, patches, IP support, and more. Please check back often for the most current information.


Software Requirements
  • ISE Design Suite 14.3 or Vivado Design Suite 2012.3, available on the Xilinx Download Center, is required for use of General ES silicon forArtix-7 devices
  • Patches - this is the complete list of available patches for ISE14.3/Vivado 2012.3 software targeting the Artix-7 General ES silicon
      • Required patches for all users:
        • None
      • Required patches based on usage:
        • None
Software Known Issues
  • (Xilinx Answer 47816) - 7 Series - ISE 14.x/Vivado 2012.x Design Suite Known Issues Related to 7 Series FPGAs
Other Important Items
  • (Xilinx Answer 51017) - 7 series FPGAs GTP Transceiver Power-up/Power-down
  • (Xilinx Answer 51369) - Design Advisory for the Artix-7 FPGA GTP Transceiver - Attribute Updates, Issues, and Work-arounds for Initial/General Engineering Sample (ES) Silicon

Revision History
09/26/2012 - Initial Release

AR# 52049
Date Created 09/26/2012
Last Updated 10/23/2012
Status Active
Type Known Issues