We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 52442

2012.3 Vivado - PinPlanning: Differential ports are getting placed in wrong sites when dragging and dropping to package view of elaborated design


I have created a design with differential ports.

When I open the elaborated design, the I/O Ports tab shows the expected differential signals as type LVDS* and it shows the expected port name under Neg Diff Pair

When dragging and dropping the differential port pair, the ports are not placed onto a matching P side and N side port location as expected.

The pins are split up and placed onto unrelated P and N pins or onto two P side pins.

After saving and running the design, I see the following DRC warning:

Differential terminals <signal>_p,<signal>_n placed at <>,<> are of incompatible polarities.

Can you please let me know how to overcome this?


This issue is only seen when trying to do I/O planning by opening an elaborated design.

The ports will be placed properly if placed in the synthesized design.

This issue has been resolved in Vivado 2013.1 and up.
AR# 52442
Date Created 11/30/2012
Last Updated 09/29/2014
Status Active
Type Known Issues
  • Virtex-7
  • Vivado Design Suite - 2012.2