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AR# 52632

Vivado Simulator - How to generate a .saif file for power analysis in Vivado Simulator


How can I generate a .saif file in Vivado XSIM?


Follow the steps below to generate the .saif file.
1.    Run the post implementation functional simulation using only Verilog netlists, not VHDL.
2.    After opening the functional simulation in XSIM, type these commands in the Tcl console:
log_saif [get_object /<toplevel_testbench/uut/*>]
run *ns

When using the log_saif command it will only log the signals specified in the argument, it does not by default log the signals being seen in the simulation waveform view.

If you wish to observe specific signals or internal signals you need to specifically add them, the following is an example of how to do this:
set top_level [get_obj]
Run this when top_level TB is selected.
set my_int_signal1 [get_objects {/my_TB/uut/Module_1/sub_module1/CLK}]
set my_int_signal2 [get_objects {/my_TB/uut/Module_1/sub_module3/EN}]

set saif_signals [get_obj $top_level $my_int_signal1 $my_int_signal2]
This combines all of the signals defined above into one variable.
log_saif [get_objects $saif_signals]
This will log the combined signals into your .saif file.
run xx ns

Alternatively you can do as follows:
log_saif [get_objects $top_level]
log_saif [get_objects $my_int_signal1]
log_saif [get_objects $my_int_signal2]

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58882 Xilinx Simulation Solution Center - Design Assistant - Vivado Simulator - Behavioral Simulation N/A N/A
AR# 52632
Date Created 12/04/2012
Last Updated 11/18/2014
Status Active
Type General Article
  • Vivado Design Suite