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AR# 52860

14.4 EDK, AXI Infrastructure - How do I connect different bus protocols? Which bridges are available?


How do I connect peripherals with different bus standard protocols?


Xilinx provides bus IP to enable connectivity between different bus interface protocols.

The following processor bus bridges are currently offered as part of the Embedded Development Kit (EDK):

  • AHB-Lite to AXI Bridge
  • AXI to AXI Connector and AXI Interconnect
  • AXI4 to AHB-Lite Bridge
  • AXI Chip to Chip Bridge
  • AXI to PLBv46 Bridge
  • PLBv46 to AXI Bridge

For more information on the different types of bridges and their specifications, please reference their individual data sheets. Documentation for Xilinx IP can be found on the Product Support & Documentation page.

Additionally, Vivado users can make use of the AXI Protocol Converter; it connects one AXI4, AXI3, or AXI4-Lite master to one AXI slave of a different AXI memory-mapped protocol.

AR# 52860
Date Created 02/14/2013
Last Updated 02/14/2013
Status Active
Type General Article
  • Zynq-7000
  • FPGA Device Families
  • Vivado
  • ISE Design Suite
  • PlanAhead
  • More
  • AXI Interconnect
  • AXI to AXI Connector