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AR# 53167

Virtex-5 - IO Standard for SPI/BPI PROM interface on device

Description

Virtex-5 configuration I/Os use LVCMOS_12F as the default standard as defined in the Virtex-5 Configuraiton Guide UG191.

What is the I/O Standard for PROM interface on the device?

Solution

The chosen FPGA configuration mode places some constraints on the FPGA application, specifically the I/O voltage allowed on the FPGA's configuration banks. 

For example, the SPI or BPI modes leverage third-party flash memory components that are usually 3.3V-only devices (but tolerant of lower voltages). 

This requires that the I/O voltage on the bank or banks attached to the memory must comply with the input voltage.

We use LVCMOSxx_12F whatever that bank voltage is set to in order to comply with PROM.

For example for 3.3V PROM, bank voltage is set to Vcco = 3.3V and IOSTANDARD is set to LVCMOS33_12F.

AR# 53167
Date Created 11/28/2012
Last Updated 07/30/2014
Status Active
Type General Article
Devices
  • Virtex-5