Is there a switch in the Vivado tool to instruct Implementation to not trim away unconnected logic (similar to the -u MAP switch in ISE)?
This can be done during Vivado logic optimization (opt_design). The opt_design command performs the following optimizations by default:
Sweep removes the cells that have no loads. To restrict sweep optimization that is run by default, use the following command in a Vivado Tcl script:
opt_design -retarget -propconst -bram_power_opt
In Project mode, -retarget -propconst -bram_power_opt should be added in the "More Options" field under the "Opt Design (opt_design)" section of the Implementation settings.
For more details, Check the topic "Logic Optimization" in the Vivado Implementation user guide (UG904).