This answer record shows the support of some of the Vivado synthesis properties in XDC:
MARK_DEBUG, KEEP_HIERARCHY, IOB, USE_DSP48
Example codes and constraints are attached to the end of this answer record.
This property tells the tool that certain nets will be used for debugging purpose.
Example: set_property MARK_DEBUG TRUE [get_nets u/temp*]
This property is working in the current version of the tool but the report does not mention that the property is set.
The property/attribute is used to prevent optimizations along the hierarchy boundaries.
This can only be set in the RTL and not via XDC.
This property tells the tool that a register should be packed into IOB during implementation.
The application of this property on ports is now possible in the current version of Vivado
Example set_property IOB TRUE [get_ports out*]
This property is working in the current version of the tool and can be set via XDC.
This property instructs the synthesis tool how to infer arithmetic structures, namely in the use of DSP48 primitives.
Example: set_property use_dsp48 yes [get_nets sum*]
This property is supported in the current version of the tool and can be set via XDC.
Codes and Constraints examples:
|Coding example name||Property|