I am trying to pack four RAM32x1D on to the same slice.
ISE Design Suite was able to pack this successfully using RLOCs.
Vivado fails to pack them and gives critical warnings similar to the following:
Is there any way to work around this?
This is due to an issue with Vivado not being able to follow RLOC constraints on RAM32x1Ds correctly.
This is assigned to be fixed in the 2015.1 release of Vivado Design Suite.