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AR# 56078

JESD204B v4.0 - Updated RX Buffer settings for 7 Series FPGA GTX, GTP and GTH

Description

The RX Buffer can sometimes indicate an underflow on RXBUFSTATUS as the buffer full level drops below the underflow threshold. The buffer does not always completely empty and cause data errors, but the buffer settings should be updated to improve reliability and prevent the possibility of underflow.

Solution

Update the following GTX, GTP and GTH settings to ensure there is enough space in the buffer to prevent underflow:

CLK_COR_MIN_LAT = 8
CLK_COR_MAX_LAT = 12
RXBUF_THRESH_UNDFLW = 3
RXBUF_THRESH_OVRFLW =57
RXBUF_THRESH_OVRD = TRUE


Note that the total receive latency is increased by 5 byte clock periods after this change is made.

Revision History:
06/20/2013 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54480 LogiCORE IP JESD204 - Release Notes and Known Issues for Vivado 2013.1 and newer tools N/A N/A
AR# 56078
Date Created 05/20/2013
Last Updated 06/20/2013
Status Active
Type General Article
IP
  • JESD204