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AR# 56155

MIG 7 Series - KC705 dual rank example design


When implementing a dual rank DDR3 design on the KC705, the board pinout will not pass the MIG verification tool.   You receive an error message stating that the following pin out rule from UG586 is violated:

     If multiple CK outputs are used, such as for dual rank, all CK outputs must come from the same byte lane.

The rule above was added in MIG 7 Series v1.6, after further characterization data proved this requirement was necessary.  The KC705 evaluation board violates this requirement, as it was designed and built well before this requirement existed. While the KC705 violates this requirement, we have not had any reported issues with tIS/tIH violations and believe this violation can be ignored for KC705 evaluation purposes only. However, the top level parameters will have to be modified manually in order to use the dual rank pin out on the KC705.


Due to the violation pin out verification, users will not be able to successfully generate a Dual Rank design targeting the KC705 pinout. Therefore, a default design must be generated and the top-level parameters and XDC constraints must be manually modified. Attached is a MIG 7 Series dual rank DIMM example design targeting the KC705, which can be used for evaluation purposes only.


Associated Attachments

Name File Size File Type
example_project.zip 19 MB ZIP

Linked Answer Records

Associated Answer Records

AR# 56155
Date Created 05/27/2013
Last Updated 07/02/2013
Status Active
Type General Article
  • Kintex-7
  • MIG 7 Series
Boards & Kits
  • Kintex-7 FPGA KC705 Evaluation Kit