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AR# 56393

2013.4 Vivado Timing - Explanation for "Source Offset to Center" in Report_Datasheet

Description

When I run report_datasheet on my design, I do not understand how the column Source Offset to Center is being calculated on a bus.

Solution

The Source Offset to Center is the difference between the center of the data eye to the center of the data capture window based upon worst case setup and hold times of the input pad.

To calculate the Source Offset to Center for each bit:

  1. Define window #1 as bounded by the setup and hold window of the input pad. For example, if the setup time was 2 ns and the hold time was 1 ns, this creates a window from 2 ns before the capture clock edge to 1 ns after the capture clock edge during which the input data must be stable to be captured. The center of this window would be 0.5 ns before the capture clock edge.
  2. Define window #2 as bounded by the complement of the window defined by a -max and -min set_input_delay constraint. For example, if the clock period was 10 ns with a -min input delay of 1 ns and a -max input delay of 2 ns, this creates a window from 8 ns (10 ns - 2 ns) before the capture clock edge to 1 ns after the capture clock edge. The center of this window would be 3.5 ns before the capture clock edge.

The Source Offset to Center is then calculated by subtracting window #1 from window #2.

In the above example, it would be 3.5 ns - 0.5 ns = 3 ns. Ideal Source Offset to Center would be 0 ns, and it may be beneficial to add an additional 3 ns of set_input_delay.

AR# 56393
Date Created 06/13/2013
Last Updated 01/17/2014
Status Active
Type General Article
Devices
  • FPGA Device Families
Tools
  • Vivado Design Suite