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AR# 56937

System Generator - The setting of Clock Pin locations in subsystem System Generator tokens will be ignored in the Multiple Subsystem Generator flow

Description

I have a Multiple Subsystem Generator design where there are two subsystems which both have their own clock locations defined in their respective System Generator tokens. However, when I look in the ISE project incorporating the generated Multiple Subsystem Generator design, after implementation, the selected pins are not chosen for the respective clocks from each subsystem.

When I reviewed messages in the Matlab console, I found messages related to these LOCs being ignored in the Multiple Subsystem Generator flow.

Warning: The subsystem 'Top_Design/Subsystem' specifies a clock pin location (A9). This location constraint is ignored
in the multiple subsystem generation flow. 

How do I get the clocks correctly placed?

Solution

As the message highlights, this is expected behavior in the Multiple Subsystem Generator flow. It is necessary to add a UCF file to the overall ISE project to include the necessary LOC constraints.

For example, based on above warning: 

NET "subsystem_cw_clk" LOC = A9;

AR# 56937
Date Created 07/31/2013
Last Updated 07/31/2013
Status Active
Type General Article
Tools
  • System Generator for DSP - 14.1
  • System Generator for DSP - 14.2
  • System Generator for DSP - 14.3
  • More
  • System Generator for DSP - 14.4
  • System Generator for DSP - 14.5
  • System Generator for DSP - 14.6
  • Less