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AR# 57083

2014.x Vivado Hierarchical Design - "WARNING: [Timing 38-242] The property HD.CLK_SRC of clock port "clk" is not set..."

Description

I have set up two create_clock constraints, one for the input 'clk' and one for the input 'sw_clk'. 

When I run in OOC mode I receive warnings indicating that the two clocks mentioned are not constrained.  

Why does the warning messages occur?

WARNING: [Timing 38-242] The property HD.CLK_SRC of clock port "clk" is not set. In out-of-context mode, this prevents timing estimation for clock delay/skew

Solution

First, check if the constraints are being picked up by the tool.

Use the below command after opening the implemented design (of OOC module) to check this.

report_clocks

If the above command returns the clock signals and their period values then the below is applicable.

The signals "clk" and "sw_clk" do not have the HD.CLK_SRC constraint and so the tool is issuing a warning as a result of the missing HD constraint. 

If the HD.CLK_SRC property is not set, no clock delay is used during timing analysis. 


When you set the HD.CLK_SRC constraints in XDC for the OOC module, the warnings are not seen.


 

AR# 57083
Date Created 08/13/2013
Last Updated 01/14/2015
Status Active
Type General Article
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
Tools
  • Vivado Design Suite - 2013.2