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AR# 57083

Vivado Hierarchical Design Partial Reconfiguration - "WARNING: [Timing 38-242] The property HD.CLK_SRC of clock port "clk" is not set..."


I have set up two create_clock constraints, one for the input 'clk' and one for the input 'sw_clk'. 

When I run in OOC mode I receive warnings indicating that the two clocks mentioned are not constrained.

Why does the warning messages occur?

WARNING: [Timing 38-242] The property HD.CLK_SRC of clock port "clk" is not set. In out-of-context mode, this prevents timing estimation for clock delay/skew


First, check if the constraints are being picked up by the tool.

Use the following command after opening the implemented design (of OOC module) to check this.


If the above command returns the clock signals and their period values then the below is applicable.

The signals "clk" and "sw_clk" do not have the HD.CLK_SRC constraint and so the tool is issuing a warning as a result of the missing HD constraint.

If the HD.CLK_SRC property is not set, no clock delay is used during timing analysis.

When you set the HD.CLK_SRC constraints in XDC for the OOC module, the warnings are not seen.

AR# 57083
Date 06/15/2017
Status Active
Type General Article
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Vivado Design Suite - 2013.2
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