Virtex-6 MIG DDR3 designs targeting single rank x8 RDIMMs incorrectly included two sets of ODT and CS signals.
These parts only use one CS_n and one ODT. Manual modifications to the RTL and UCF are outlined in this answer record.
Version Fixed: Not to be Fixed.
Please follow the below procedure to work around this limitation. The issue is present under ISE14.7 (v3.92)
To change the RTL to only include one CS_n pin and one ODT pin:
Locate the pin LOC for the "ddr3_cs_n" pin and comment out the line. This pin is not needed for single rank RDIMM designs.