We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 57561

Example Design - Using the AXI DMA in polled mode to transfer data to memory


Attached to this Answer Record is an Example Design for using the AXI DMA in polled mode to transfer data to memory.


This design targets Zynq devices and uses a simple counter to drive the S2MM channel of the AXI DMA.

Counter data is sent into and then read out of memory, and is finally sent out of the MM2S channel to an AXI Streaming FIFO.

The data received by the AXI Streaming FIFO is verified against the counter data.

The ARM controls DMA transfers via GP ports by accessing the AXI DMA core through its AXI Lite interface.

It uses simple polling of the status register to manage DMA transfers.

For more details about the design, refer to the dma_ex_polled/doc directory.

The current version of this design was created in Vivado 2015.1.


Associated Attachments

Name File Size File Type
dma_ex_polled_v2_1.zip 1 MB ZIP
simple_dma.xpr.zip 32 MB ZIP

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
57550 Example Designs - Designing with the AXI DMA core N/A N/A
AR# 57561
Date 05/18/2018
Status Active
Type General Article
  • Zynq-7000
  • Vivado Design Suite - 2013.2
  • AXI DMA Controller
  • AXI DMA Controller
  • AXI Streaming FIFO
  • More
  • AXI Interconnect
  • AXI Interconnect
  • Less
Boards & Kits
  • Zynq-7000 SoC Boards and Kits
Page Bookmarked