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AR# 57739

Xilinx HSSIO Solution Center - Design Assistant Debugging Comma Alignment, TX/RX Buffer or Buffer Bypass Problems


This answer record is a guide to debugging the Comma Alignment, TX/RX buffer or buffer bypass problems.

Note: This answer record is part of the Xilinx HSSIO Solution Center (Xilinx Answer 37181).

The Xilinx HSSIO Solution Center is available to address all questions related to HSSIO.

Whether you are starting a new design or troubleshooting a problem, use the HSSIO Solution Center to guide you to the right information.


Comma Detection and Alignment

Serial data must be aligned to symbol boundaries before it can be used as parallel data. Without proper alignment, the incoming 8B10B data will not decode correctly. 

If alignment is lost at any time, there will be a burst of disparity (RXDISPERR) and not in table (RXNOTINTABLE) errors.

Make sure that the final "target" alignment is one that corresponds to Table 4-33 in the user guide (shown below).

RXSLIDE can be used to override the automatic comma alignment and to shift the parallel data.

RXSLIDE is driven High for one RXUSRCLK2 cycle to shift the parallel data by one bit. Be aware that RXSLIDE must be Low for at least 32 RXUSRCLK2 cycles before it can be used again.

Key Points

  • Make sure that both RX and TX are assigned the same comma value.
  • If there is no valid data when RXBYTEISALIGNED is High, then check the status of RXPCOMMAALIGNEN/RXMCOMMAALIGNEN because these attributes must be set High to detect comma alignment.
  • RXCOMMADET should be monitored as it will RXcomadeten. Disable after alignment with rxcommaen.
  • RXBYTEREALIGN can also be monitored as it detects misalignments.
  • For 7 series GTX/GTH: In applications that operate at a line rate greater than 5 Gb/s and have excessive noise in the system, the byte align block might falsely align to a wrong byte boundary and falsely assert the RXBYTEISALIGNED signal when no valid data is present.
    In such applications, a system-level check should be in place for checking the validity of the RXBYTEISALIGNED indicator and data.
  • For UltraScale using DFE equalization, when LPM is called for can lead to intermittent data and alignment errors. See (Xilinx Answer Record 64195)
  • In systems that use the RX OOB block, such as PCIe and SATA, after locking to a valid byte boundary and asserting the RXBYTEISALIGNED signal, the byte align block might occasionally deassert the RXBYTEISALIGNED signal even when there is no change in the byte boundary.
    In such applications, RXBYTEISALIGNED should not be used as a valid indicator of the change in byte boundary after the first assertion.

Useful Answer Records

(Xilinx Answer 46200) RXBYTEISALIGNED is not always reliable
(Xilinx Answer 47054) User defined comma for SONET not allowed
(Xilinx Answer 43242) GTX RXSLIDE does not work in simulation with 13.1
(Xilinx Answer 50530) Can RXBYTEREALIGN be used as RXSLIDE completion status signal?

Clock Correction

Very few problems are reported with Clock Correction for the 7 series. The user guide explains it well and the example designs do a good job of setting it up.

Useful Debug Ports

  • RXBUFSTATUS - Indicates when correction should be applied.
  • CLK_CORRECT_USE - Indicates if clock correction is turned On.
  • RXCLKCORCNT - Shows clock correction activity.

TX/RX Buffer

The TX/RXBUFSTATUS should be monitored to make sure that the buffers do not overflow. If and when they do, data will be lost. 

The following are the potential causes:

  • A reset sequence (or lack thereof) that does not reset the TX/RX buffer
  • For RX, not enough clock correction sequences available to correct for the amount of frequency difference in the incoming and onboard clocks. (The clocks that drive the 2 sides of the buffer.)
  • For TX buffer, the XCLK (TXOUTCLK) domain and the Fabric (TXUSRCLK) clock domain are not based on the same oscillator.

Buffer Bypass

Buffer bypass is an advanced use mode and should only be used if low latency is required. The 7 series has had some problems with the TX phase initialization. 

These should all be fixed in ISE 14.7 and Vivado 2013.3 design tools; see (Xilinx Answer 55009), (Xilinx Answer 57382), and (Xilinx Answer 54804).

Useful Debug Ports

  • TX/RX_BUFEN - Is the buffer being used?
  • For phase alignment, set up ChipScope (or a simulation) to capture the phase alignment process shown in the User's Guide. For example, in (UG476) Figure 3-20 for TX buffer bypass in single lane manual mode.

Xilinx Answer Records

(Xilinx Answer 43883) How does RXCDRLOCK work?

Application Notes

Non Integer Data Recovery Unit (XAPP875) - The NI-DRU extends the lower data rate limit to 0 Mb/s and the upper limit to 1,250 Mb/s, making embedded high-speed transceivers the ideal solution for true multi-rate serial interfaces.

AR# 57739
Date Created 09/30/2013
Last Updated 10/01/2015
Status Active
Type Solution Center
  • Artix-7
  • Kintex-7
  • Virtex-7
  • More
  • Kintex UltraScale
  • Virtex UltraScale
  • Less