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AR# 57741

Xilinx HSSIO Solution Center - Design Assistant Debugging Channel Bonding or 8B/10B Problems


This answer record contains debugging tips concerning channel bonding and the 8B/10B encoder/decoder.

Note: This answer record is part of the Xilinx HSSIO Solution Center (Xilinx Answer 37181).

The Xilinx HSSIO Solution Center is available to address all questions related to HSSIO. 

Whether you are starting a new design or troubleshooting a problem, use the HSSIO Solution Center to guide you to the right information.


Channel Bonding

Most problems encountered with channel bonding are not caused by the channel bonding circuitry itself. This is one of the first steps in receiving a signal, and if there are problems with the channel setup, they can cause channel bonding to fail.

Make sure there is a good REFCLK, clean power supplies, and a solid data eye; Bit Errors can be a problem for channel bonding. 

As with all debug, the user guide should be your reference to make sure that the setup is correct. 

For 7 series and UltraScale FPGAs, check the following:

  • The data encoding must be supported (i.e., 8B10B).
  • The RXCHBONDSEQ, RXCHBONDMASTERS, RXCHBONDSLAV, RXBUF_EN is TRUE. Make sure to be aware of how the CHAN BOND_SEQ_X_Y is encoded. It is not just a straight bit sequence.
  • The RXCHBONDO and RXCHHBONDI are connected correctly (see examples in UG). These can be seen in the RTL or the schematic editor.
  • The RXCHBONDLEVELS are set correctly.
  • The amount of time between Channel Bonding sequences is compatible with the CHAN_BOND_MAX_SKEW setting. Using the wizard defaults is usually safe, but be aware that changes to the design can require changes to this setting.
    • A caveat here is that the actual maximum skew must be less the CHAN_BOND_MAX_SKEW setting.
      If not, the correction will be applied in the wrong direction and the channels will bond out of sync by the length of time between channel bonding sequences (the channel will sync to the wrong comma).

A common question on Channel Bonding is how many lanes can be bonded. It will vary with clock rate and other conditions. The limiting factor is meeting timing for the RXUSRCLK. 

As long as the RXUSRCLK timing constraint is met, the design is viable. Using the lane closest to the middle as the master will make meeting timing easier.

8B10B Encoder/Decoder

The encoder/decoder has proven to be very reliable. Disparity and "Not in Table" errors are normally the result of bit errors or alignment issues. 

A bit error or misalignment is the root cause and the normal course is to debug those problems first. If errors are occurring in "batches," it would be an alignment issue and the occasional error would be caused by a bit error. 

Monitoring RXBYTEISALIGNED can help in determining the cause, often caused by a lack of margin in the data eye; see (Xilinx Answer 57743) - Debugging Equalization and Margin Problems.

For 7 series and UltraScale FPGAs, if you are not using 8B10B, or if it is turned off, be aware that mapping of the RXDATA bits changes.

Not all of the bits are data in that case. See the 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476), Table 4-51 for the layout, for UltraScale GTH see (UG576) table 4-46 in the RX interface section and for GTY (UG578), see table 4-46 in the RX Interface section.

AR# 57741
Date 09/23/2015
Status Active
Type Solution Center
  • Artix-7
  • Kintex-7
  • Virtex-7
  • More
  • Kintex UltraScale
  • Virtex UltraScale
  • Less
  • 8b/10b Encoder
  • 8b/10b Decoder
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