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AR# 57764

7 Series Integrated Block Wrapper for PCI Express v2.2 - TX de-emphasis setting is not set correctly on Lane 1 through Lane 7 in VHDL version of the core

Description

Version Found: v1.10/v2.1
Version Resolved and other Known Issues

See (Xilinx Answer 40469) for v1.10
See (Xilinx Answer 54643) for v2.1

When 7 series Integrated Block Wrapper for PCI Express is generated in VHDL language, Lane 1 through Lane 7 have TX de-emphasis of -6dB while Lane 0 is adaptive (-3.5dB or -6dB) depending on the negotiated de-emphasis level and the link speed.

This issue only arises when the core is generated by selecting VHDL language; the Verilog version of the core does not have this issue.

Solution

To work around this issue, in the <core_name>_gt_top.vhd module, make the following changes:

From:

 -- Generate TX Deemph input based on Link Width
  tx_deemph_x1 : if (LINK_CAP_MAX_LINK_WIDTH_int = 1) generate
    pipe_tx_deemph_concat(0) <= pipe_tx_deemph;
  end generate;

  tx_deemph_x2 : if (LINK_CAP_MAX_LINK_WIDTH_int = 2) generate
    pipe_tx_deemph_concat <= ("0" & pipe_tx_deemph);
  end generate;

  tx_deemph_x4 : if (LINK_CAP_MAX_LINK_WIDTH_int = 4) generate
    pipe_tx_deemph_concat <= ("000" & pipe_tx_deemph);
  end generate;

  tx_deemph_x8 : if (LINK_CAP_MAX_LINK_WIDTH_int = 8) generate
    pipe_tx_deemph_concat <= ("0000000" & pipe_tx_deemph);
  end generate;

To:

-- Generate TX Deemph input based on Link Width 
tx_deemph_x1 : if (LINK_CAP_MAX_LINK_WIDTH_int = 1) generate
pipe_tx_deemph_concat(0) <= pipe_tx_deemph;
end generate;

tx_deemph_x2 : if (LINK_CAP_MAX_LINK_WIDTH_int = 2) generate
pipe_tx_deemph_concat <= (1 downto 0 => pipe_tx_deemph);
end generate;

tx_deemph_x4 : if (LINK_CAP_MAX_LINK_WIDTH_int = 4) generate
pipe_tx_deemph_concat <= (3 downto 0 => pipe_tx_deemph);
end generate;

tx_deemph_x8 : if (LINK_CAP_MAX_LINK_WIDTH_int = 8) generate
pipe_tx_deemph_concat <= (others => pipe_tx_deemph);
end generate;

Note: "Version Found" refers to the version where the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History
10/8/2013 - Initial release

Linked Answer Records

Master Answer Records

AR# 57764
Date Created 10/01/2013
Last Updated 04/28/2014
Status Active
Type General Article
IP
  • 7 Series Integrated Block for PCI Express (PCIe)