We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 57788

2013.3 Discrete Fourier Transform (DFT) v4_0 - Simulation of the DFT netlist may give different output data values to those of the C model when using XSIM or IES


If simulated using IES or XSIM, the output of the DFT core (netlist) may differ from hardware in terms of bit-accuracy of the data values versus the C model or simulation model.


This is known issue with Discrete Fourier Transform (DFT) core simulation with IES or XSIM.
The error will be an infrequent difference of the order of 1ulp, rather than a catastrophic error, as it is due to a rounding error of a single twiddle factor.
Frequency of error is low, however it can occur with any core configuration

The suggested work-around is to simulate using QUESTA/MTI.
You can tolerate these small numerical differences from the expected output depending on the application.

AR# 57788
Date 10/04/2013
Status Active
Type General Article
  • Vivado Design Suite - 2013.3
  • Discrete Fourier Transform (DFT)
Page Bookmarked