If a design with a VIO Core that is capturing data coming from a slow clock domain, the data is sometimes seen to be incorrect when the clock frequency is less than the cable speed.
If the VIO clock domain is slower than the cable clock, undesirable logic values are seen on the outputs as well.
The VIO clock needs to be faster than the cable speed in order for captured events to be buffered properly and sent back to the GUI.
The best way to work around this issue is to set the cable speed slower when you connect to the hardware session in Vivado.
If there is another debug core in the design that runs on a faster clock domain than the cable, the issue does not occur (e.g., an ILA clocked at 200MHz).
Another potential work-around is to use a faster clock to clock the VIO and to synchronize the slow data to a VIO clock domain so that the data is captured reliably.