When packaging a design with a REAL type generic / parameter in IP Packager, the parameter gets converted to SIGNED type. This results in the following error when generating output products:
The packaged VHDL design contains a VHDL generic 'real' type data as follows:
When generating this packaged IP, Vivado issues the following errors:
REAL type Generics are not supported in Vivado IP Packager. A request to add support for them has been logged, but it has not yet been scheduled.
To work around this issue, use integer data types as generic parameters when packaging IP.