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AR# 58312

Zynq-7000 DDRC - DRAM_burst8_rdwr ddrc register (0xF8006034) sets incorrect number of clock cycles for init sequence


Vivado/XPS sets the DRAM_burst8_rdwr register (Address 0xF8006034) to "0x00010014". The TRM specifies that bits 13:4 (reg_ddrc_pre_cke_x1024) set the number of clock cycles to wait before driving CKE High to start the DRAM init sequence. The tools set this field to 1, or a value of 1024 clock cycles (~2 microseconds). However, the JEDEC DDR3 standard requires that this wait period be 500 microseconds:

JEDEC Standard No. 79-3F, Power-Up Initialization Sequence section 3.3.1:

After RESET# is de-asserted, wait for another 500 us until CKE becomes active. During this time, the DRAM will start internal state initialization; this will be done independently of external clocks.

Therefore, bits 13:4 of the DRAM_burst8_rdwr register should be set to "0x105", or 267264 clock cycles (500 microseconds).


In order to adhere to the JEDEC specification, change bits 13:4 of the DRAM_burst8_rdwr register to "0x105".

This issue has been fixed in the Vivado 2013.3 tool release.

AR# 58312
Date Created 11/07/2013
Last Updated 11/12/2013
Status Active
Type General Article
  • Zynq-7000
  • Vivado Design Suite
  • EDK - 10