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AR# 58435

DDR4, DDR3, QDRIV, QDRII+, RLDRAM3 UltraScale and UltraScale+ - IP Release Notes and Known Issues for Vivado 2014.1 and newer tool versions

Description

This answer record contains the Release Notes and Known Issues for the DDR4, DDR3, QDRII+, QDRIV, RLDRAM3 UltraScale Cores and includes the following:

  • Supported Devices
  • General Information
  • Known Issues
  • Revision History

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2014.1 and newer tool versions.

Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.

MIG IP Page:

http://www.xilinx.com/content/xilinx/en/products/intellectual-property/mig.html

Solution

General Information

Supported devices can be found in the following locations:

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado tools.

Table 1 correlates the core version to the first Vivado design tools release version in which it was included.

Table 1: Version

DDR4 VersionDDR3 VersionRLDRAM3 VersionQDRII+ VersionQDRIV VersionVivado Tools Version
v2.1v1.3v1.3v1.3v1.22016.3
v2.0 Rev1v1.2 Rev1v1.2 (Rev. 1)v1.2 (Rev. 1)v1.1 (Rev. 1)2016.2
v2.0v1.2v1.2v1.2v1.12016.1
v1.1v1.1v1.1v1.1v1.02015.4
v1.0v1.0v1.0v1.02015.3
v7.1v7.1v7.1v7.12015.2
v7.0v7.0v7.0v7.02015.1
v6.1v6.1v6.1v6.12014.4
v6.0v6.0v6.0v6.02014.3
v5.0 Rev1v5.0 Rev1v5.0 Rev1v5.0 Rev12014.2
v5.0v5.0v5.0v5.02014.1


* Starting with the release of Vivado 2015.3, the MIG wizard is no longer used. A separate wizard exists for all supported memory interface types. Therefore, the core versions reset to 1.0.

For a list of supported memory interfaces and features for UltraScale FPGAs, see the LogiCORE IP UltraScale Architecture-Based FPGAs Memory Interface Solutions Product Guide (PG150) located at:

http://www.xilinx.com/products/technology/memory-interfacing/index.htm

For a complete list of supported memory devices please refer to the attached spreadsheet called "memory_device_support_2016_1.xlsx".


For a list of supported frequencies for UltraScale FPGAs Memory Interfaces, see the appropriate DC and Switching Characteristics Data Sheet available in the UltraScale Documentation Center.

For supported simulators, see the Xilinx Design Tools: Release Notes Guide.

The MIG tool includes the appropriate frequency range for each specific memory interface configuration

Table 2 provides answer records for general guidance when using the MIG UltraScale core.

Table 2: General Guidance

Answer RecordTitle
(Xilinx Answer 59625)MIG UltraScale - Design Methodology Checklist
(Xilinx Answer 61304)MIG UltraScale - Clocking Guidelines and Requirements
(PG150) - DebuggingMIG UltraScale DDR4/DDR3 - Hardware Debug Guide
(Xilinx Answer 63462)MIG UltraScale - Sample CSV data file for creating Custom Parts
(Xilinx Answer 63831)MIG UltraScale - Migrating and Upgrading IP into 2015.1


Known and Resolved Issues

The following table provides known issues for the MIG UltraScale core, starting with v5.0, initially released in the Vivado 2014.1 tool.

Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

MIG UltraScale DDR4 SDRAM

The following table provides known issues for MIG UltraScale DDR4.

Note: The "Version Found" column lists the version the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer RecordTitleVersion FoundVersion Resolved
(Xilinx Answer 68143)DDR4 IP - IP GUI hangs and crashes for specific settingsv2.1Not Resolved
(Xilinx Answer 67956)DDR4/DDR3 UltraScale IP - Supported configurations for Self Refresh and Save/Restorev2.1Not Resolved
(Xilinx Answer 67979)DDR4 UltraScale IP - Design generation error occurs due to incorrect maximum MMCM VCO value for -1H speed gradev2.1Not Resolved
(Xilinx Answer 67967)UltraScale Memory IP - Error: [Unisim MMCME3_ADV-10] The calculated PFD frequency=799.360512 Mhz. This exceeds the permitted PFD frequency range v2.1Not Resolved
(Xilinx Answer 67957)
UltraScale Memory IP - "Phy core regeneration & stitching failed" occurs when opening an older Vivado project without upgrading the Memory IPv2.1Not Resolved
(Xilinx Answer 67933)
UltraScale Memory IP - Error messages generated after archiving and moving a project containing Memory IP with a custom part.v2.1Not Resolved
(Xilinx Answer 67891)DDR4/DDR3 IP - Ping-Pong PHY behavioral simulations fail with data errors when using BFM simulation modev2.0 (Rev. 1)Not Resolved
(Xilinx Answer 67392)UltraScale and UltraScale+ Memory IP - pulse width violations can occurv2.0 (Rev 1)Not Resolved
(Xilinx Answer 67230)UltraScale DDR4 SDRAM IP - tREFI interval is incorrectly setv2.0Not Resolved
(Xilinx Answer 66471)DDR4 IP - Incorrect Write Recovery (WR) value programmed to Mode Register 0 (MR0)v1.1Not Resolved
(Xilinx Answer 67544)DDR4/DDR3 UltraScale IP - Data errors seen at user interface when using Normal Ordering Error. The errored data presented is correct data from a later read from the same address. App_rdy might get stuck low.Initial Release
v2.1
(Xilinx Answer 67684)UltraScale Memory IP - moving IP that uses custom memory parts (CSV) might cause problemsv2.0 (Rev. 1)v2.1
(Xilinx Answer 67631)UltraScale DDR4 IP - some parts use the incorrect memory speed gradev2.0 (Rev. 1)v2.1
(Xilinx Answer 67455)UltraScale DDR3 and DDR4 IP - ECC signals are missing from the User Interface when ECC is enabled without AXIv2.0 (Rev. 1)v2.1
(Xilinx Answer 67335)UltraScale+ Memory IP - devices fail during opt_design with custom memory part if generation of the IP output products is skippedv2.0 (Rev. 1)v2.1
(Xilinx Answer 67255)UltraScale and UltraScale+ DDR4 SDRAM IP - [Place 30-487] error may occur for some configurationsv2.0v2.1
(Xilinx Answer 67008)DDR4 UltraScale - Enabling DBI Read causes Read Complex register values in XSDB BRAM to not be populatedv2.0v2.1
(Xilinx Answer 66951)Memory IP - WARNING: [DRC 23-20] Rule violation (PDCN-1569) LUT equation term checkv2.0v2.1
(Xilinx Answer 66938)DDR4 UltraScale+ - Usage of six or more DDP (Dual Die Package/Twin Die) components is limited to 2133Mbps operation. This limit is not adhered to within the DDR4 Wizard. Manual adherence to this limit requiredv2.0v2.1
(Xilinx Answer 66360)UltraScale Memory IP - Core Container does not include *.csv file when a custom memory part is createdv1.1v2.1
(Xilinx Answer 67225)UltraScale Memory IP - CLOCK_DEDICATED_ROUTE BACKBONE constraint not automatically generated by IPv2.0v2.0 Rev1
(Xilinx Answer 67224)UltraScale Memory IP - CLOCK_DEDICATED_ROUTE BACKBONE constraint must be applied to the CLKIN1 pin of the MMCMv2.0v2.0 Rev1
(Xilinx Answer 67164)UltraScale+ Memory IP - timing failures occur due to high congestion levelsv2.0v2.0 Rev1
(Xilinx Answer 67054)DDR4 IP - Extra CK/CK# clock pair generated for 3DS RDIM part M393A8K40B21-CTCv2.0v2.0 Rev1
(Xilinx Answer 66937)DDR4 and DDR3 IP - UNISIM simulations fail when using Self Refresh and Self Restore optionsv2.0v2.0 Rev1
(Xilinx Answer 66927)DDR4 and DDR3 IP - BFM simulations have errors when using Self Refresh and Self Restore optionsv2.0v2.0 Rev1
(Xilinx Answer 66678)UltraScale Memory IP - Design fails during 'opt_design' when using Custom CSVv1.1v2.0 Rev1
(Xilinx Answer 66554)DDR4 IP - a 300MHz reference input clock cannot be chosen for 1333MHz (750ps) output clock frequencyv1.1v2.0 Rev1
(Xilinx Answer 65083)DDR4/DDR3 SDRAM IP - No DIMM support for XCZU2EG and XCZU3EG devices with the SBVA484 packagev1.0v2.0 Rev1
(Xilinx Answer 64774)MIG UltraScale DDR4 - SETUP/HOLD violations in the mmcm_clkout0 domainv7.0v2.0
(Xilinx Answer 65950)MIG UltraScale DDR4/DDR3 - Synplify PRO Synplify Pro Black Box Testing designs might fail in calibration v1.0v2.0
(Xilinx Answer 65372)DDR4/DDR3 IP - Vivado GUI Simulations fail with data errors when using VCS simulatorv1.0v2.0
(Xilinx Answer 64784)MIG UltraScale DDR4 - false DRC MIG-32# errors detected for sys_clk_p/nv7.0v2.0
(Xilinx Answer 62543)MIG UltraScale - Certain speed grades incorrectly prevent previously allowed input clock periodsv6.0v2.0
(Xilinx Answer 65327)UltraScale Memory IP - CRITICAL WARNING: [Xicom 50-38] xicom: The current version of Vivado does not support this detected version of the MIG core. 2015.2 is the last version supporting it.v1.0NA
(Xilinx Answer 64778)MIG UltraScale - When using the Auto Assign feature of Bank Planner, an error message is not issued when the memory ports do not fit into a half bankv7.0v1.1
(Xilinx Answer 65431)UltraScale Memory IP - Designs generated pre-v1.0 with "No Buffer" clocking option require path update to CLOCK DEDICTAED ROUTE constraint v1.0NA
(Xilinx Answer 65790)DDR4/DDR3 SDRAM IP - when using a Custom Memory part some timing parameters are not updated correctlyv1.0v1.1
(Xilinx Answer 65652)DDR3/DDR4 SDRAM IP - AXI enabled designs incorrectly have data mask tied to GND during Read-Modify-Writev1.0v1.1
(Xilinx Answer 65493)DDR4/3 UltraScale - IP generation fails for configurations requiring more than 3 contiguous banks when targeting FGPA devices with half banks in between full banks v1.0v1.1
(Xilinx Answer 65370)Memory IP - pblocks containing UltraScale Memory IP logic must be contained within the same clock region the memory I/O is located inv1.0v1.1
(Xilinx Answer 64188)MIG UltraScale - sys_rst missing set_false_path constraintv7.0v1.1
(Xilinx Answer 63667)MIG UltraScale DDR4 - VIOLATION: cmdWR seen for tCK = 833ps and speed bin = 833 when using Micron Memory Modelv7.0v1.1
(Xilinx Answer 62086)MIG UltraScale DDR4/DDR3 - Performance Traffic Generator only works with "ROW COLUMN BANK" Address mappingv5.0 Rev1v1.1
(Xilinx Answer 65261)MIG UltraScale DDR4/DDR3 - Dynamic DCI does not work for select devicesv7.1v1.0
(Xilinx Answer 65054)MIG UltraScale DDR4 - CAS Latency setting of 17 results in calibration failures during DQS Gate Calibrationv7.1v1.0
(Xilinx Answer 64923)MIG UltraScale - [Xicom 50-24] error message occurs after programing devicev7.0v1.0
(Xilinx Answer 64887)MIG UltraScale - Errors occur when implementing a 2015.1 MIG IP in Vivado 2015.2 - Patch available v7.0v1.0
(Xilinx Answer 64773)MIG UltraScale DDR4/DDR3 - customization GUI shows incorrect Enable Chip Select Pin option when recustomizing IPv7.0v1.0
(Xilinx Answer 64071)MIG UltraScale - custom memory parts fail simulationv7.0v1.0
(Xilinx Answer 64615)MIG UltraScale - AXI Interface Efficiency improvements for 2015.2v7.0v7.1
(Xilinx Answer 64306)MIG UltraScale DDR4 - Required calibration patch to resolve potential hardware failures due to incorrect DLL Reset during SDRAM initialization sequence (all configurations) and internal nibble clocking (x4 only) v7.0v7.1
(Xilinx Answer 64010)MIG UltraScale DDR4/DDR3 - memory controller may hang when in "Strict" modev7.0v7.1
(Xilinx Answer 64069)MIG UltraScale - The Memory Byte/Bank Planner does not honor previously set PROHIBIT pins v7.0v7.1
(Xilinx Answer 64063)MIG UltraScale DDR4/3 - DIMM tool tip incorrectly lists the density for the base component part v7.0v7.1
(Xilinx Answer 63786)MIG UltraScale - SPEC_VIOLATION tWR/tRTP tWR seen for tCK = 833ps and speed bin = 833 when using Micron Memory Modelv7.0v7.1
(Xilinx Answer 63666)MIG UltraScale DDR4 - tCK SPEC_VIOLATION for tCK = 833ps and speed bin = 833 when using Micron Memory Modelv7.0v7.1
(Xilinx Answer 64431)MIG UltraScale - ]Xicom 50-38] xicom: Invalid memory type value detected from MIG core: 0.v6.1v7.0
(Xilinx Answer 63596)MIG UltraScale - HOLD violations may be seen when using 2014.4.1v6.1v7.0
(Xilinx Answer 64070)MIG UltraScale - designs with multiple controllers may generate ERROR::34 messagev6.1v7.0
(Xilinx Answer 63261)MIG UltraScale DDR3/DDR4/QDRII+ - Multi-driver errors found during Lint checkv6.1v7.0
(Xilinx Answer 63240)MIG UltraScale DDR4/DDR3 - PHY Only Documentation - PG150 includes incorrect usage of "rdDataEn" in relation to "per_rd_done" (periodic read operation) and "rmw_rd_done" (RMW Operation)v6.1v7.0
(Xilinx Answer 62930)MIG UltraScale DDR3/DDR4 - tCCD and tRTW violations can cause data errors in multi-rank and DDR4 x16 configurationsv6.1v7.0
(Xilinx Answer 63022)MIG UltraScale DDR4/3 - Designs targeting dual rank DIMMs with address mirroring fail in hardwarev6.0v7.0
(Xilinx Answer 62776)MIG UltraScale DDR3/DDR4 - ECC fault injection does not workv6.1v7.0
(Xilinx Answer 62774)MIG UltraScale - timing failures may be seen with MIG generated example designv6.1v7.0
(Xilinx Answer 62649)MIG UltraScale - GUI allows core generation even if all address and control byte lanes have not been selectedv6.0v7.0
(Xilinx Answer 60528)MIG UltraScale DDR3 - Vivado may fail to generate output products with 64-bit data widthv5.0v7.0
(Xilinx Answer 59991)MIG UltraScale - When running QuestaSim simulation within the Vivado GUI, the simulation is not successful. v5.0v7.0
(Xilinx Answer 59989)MIG UltraScale - Critical warnings are generated when multiple MIG instances are included in a designv5.0v7.0
(Xilinx Answer 59990)MIG UltraScale - IPI MIG simulation does not have memory models available v5.0v7.0
(Xilinx Answer 62321)MIG UltraScale DDR3/DDR4 - User Interface ports direction incorrect in instantiation templatev5.0v6.1
(Xilinx Answer 61988)MIG UltraScale DDR4/3 - Hold violations might be seen on a path clocked by riu_clkv6.0v6.1
(Xilinx Answer 62050)MIG UltraScale DDR4/3 - Can reset_n be allocated to an IO or does it have to be within a memory interface bank?v5.0v6.1
(Xilinx Answer 61909)MIG UltraScale DDR3/DDR4 - app_wdf_data format clarificationv6.0v6.1
(Xilinx Answer 61076)MIG UltraScale - Multiple instances of MIG IP fail with "[Place 30-678] Failed to do clock region partitioning"v5.0 Rev1v6.1
(Xilinx Answer 60953)MIG UltraScale - Output Products must be generated before opening the IP Example Designv5.0 Rev1v6.1
(Xilinx Answer 60181)MIG UltraScale DDR4/DDR3 - Timing violations may occur at higher data rates v5.0v6.1
(Xilinx Answer 62080)MIG UltraScale DDR4 - AXI Narrow Burst simulations cause model warnings to be generatedv5.0v6.0
(Xilinx Answer 61901)MIG UltraScale DDR3/DDR4 - memory model violations observed during simulationv5.0 Rev1N/A
(Xilinx Answer 61725)MIG UltraScale DDR4 - Micron DDR4 part name shown in MIG GUI is obsoletev5.0 Rev1v6.0
(Xilinx Answer 61696)MIG UltraScale - the funcsim.v/.vhdl structural simulation model is not supportedv5.0 Rev1N/A
(Xilinx Answer 60322)MIG UltraScale DDR4 - MIG tool incorrectly allows Internal VREF to be disabled for DDR4 interfaces. Internal VREF is REQUIRED for all DDR4 interfaces. v5.0v1.1
(Xilinx Answer 59948)MIG UltraScale DDR4/DDR3 - Incorrect clock connection on dbg_hub which can have a negative timing impact.
v5.0v5.0 Rev1

 

MIG UltraScale DDR3 SDRAM

The following table provides known issues for MIG UltraScale DDR3.

Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer RecordTitleVersion FoundVersion Resolved
(Xilinx Answer 67967)UltraScale Memory IP - Error: [Unisim MMCME3_ADV-10] The calculated PFD frequency=799.360512 Mhz. This exceeds the permitted PFD frequency range v1.3Not Resolved
(Xilinx Answer 67957)UltraScale Memory IP - "Phy core regeneration & stitching failed" occurs when opening an older Vivado project without upgrading the Memory IPv1.3Not Resolved
(Xilinx Answer 67956)DDR4/DDR3 UltraScale IP - Supported configurations for Self Refresh and Save/Restore v1.3Not Resolved
(Xilinx Answer 66937)DDR4 and DDR3 IP - UNISIM simulations fail when using Self Refresh and Self Restore optionsv1.3Not Resolved
(Xilinx Answer 66927)DDR4 and DDR3 IP - BFM simulations have errors when using Self Refresh and Self Restore optionsv1.3Not Resolved
(Xilinx Answer 67933)UltraScale Memory IP - Error messages generated after archiving and moving a project containing Memory IP with a custom part.v1.3
Not Resolved
(Xilinx Answer 67891)DDR4/DDR3 IP - Ping-Pong PHY behavioral simulations fail with data errors when using BFM simulation modev1.2 (Rev. 1)Not Resolved
(Xilinx Answer 67392)UltraScale and UltraScale+ Memory IP - pulse width violations can occurv1.2 (Rev. 1)Not Resolved
(Xilinx Answer 67544)DDR4/DDR3 UltraScale IP - Data errors seen at user interface when using Normal Ordering Error. The errored data presented is correct data from a later read from the same address. App_rdy might get stuck low.v5.0v1.3
(Xilinx Answer 67455)UltraScale DDR3 and DDR4 IP - ECC signals are missing from the User Interface when ECC is enabled without AXIv1.2 (Rev. 1)v1.3
(Xilinx Answer 67684)UltraScale Memory IP - moving IP that uses custom memory parts (CSV) might cause problemsv1.2 (Rev. 1)v1.3
(Xilinx Answer 67335)UltraScale+ Memory IP - devices fail during opt_design with custom memory part if generation of the IP output products is skippedv1.2 (Rev. 1)v1.3
(Xilinx Answer 66951)Memory IP - WARNING: [DRC 23-20] Rule violation (PDCN-1569) LUT equation term checkv21.2v1.3
(Xilinx Answer 66360)UltraScale Memory IP - Core Container does not include *.csv file when a custom memory part is createdv1.0v1.3
(Xilinx Answer 67225)UltraScale Memory IP - CLOCK_DEDICATED_ROUTE BACKBONE constraint not automatically generated by IPv1.2v1.2 (Rev. 1)
(Xilinx Answer 67224)UltraScale Memory IP - CLOCK_DEDICATED_ROUTE BACKBONE constraint must be applied to the CLKIN1 pin of the MMCMv1.2v1.2 (Rev. 1)
(Xilinx Answer 67164)UltraScale+ Memory IP - timing failures occur due to high congestion levelsv1.2v1.2 (Rev. 1)
(Xilinx Answer 66678)UltraScale Memory IP - Design fails during 'opt_design' when using Custom CSV
v1.2v1.2 (Rev. 1)
(Xilinx Answer 65083)DDR4/DDR3 SDRAM IP - No DIMM support for XCZU2EG and XCZU3EG devices with the SBVA484 packagev1.0v1.2 (Rev. 1)
(Xilinx Answer 66794)UltraScale DDR3 IP - Write errors may be seen in dual rank or dual slot configurations in Vivado 2015.3 or 2015.4 due to Dynamic ODT settings v1.0v1.2
(Xilinx Answer 65950)
MIG UltraScale DDR4/DDR3 - Synplify PRO Synplify Pro Black Box Testing designs may fail in calibration v1.0v1.2
(Xilinx Answer 65421)UltraScale DDR3 - tIS memory model violations on ADDR and BA occur when simulating DDR3 example_tb testbenchv6.0v1.2
(Xilinx Answer 62543)MIG UltraScale - Certain speed grades incorrectly prevent previously allowed input clock periodsv6.0v1.2
(Xilinx Answer 65431)UltraScale Memory IP - Designs generated pre-v1.0 with "No Buffer" clocking option require path update to CLOCK DEDICTAED ROUTE constraint v1.0NA
(Xilinx Answer 65327)UltraScale Memory IP - CRITICAL WARNING: [Xicom 50-38] xicom: The current version of Vivado does not support this detected version of the MIG core. 2015.2 is the last version supporting it. v1.0NA
(Xilinx Answer 64778)MIG UltraScale - When using the Auto Assign feature of Bank Planner, an error message is not issued when the memory ports do not fit into a half bankv7.0v1.1
(Xilinx Answer 65370)Memory IP - pblocks containing UltraScale Memory IP logic must be contained within the same clock region the memory IO is located inv1.0v1.1
(Xilinx Answer 65493)DDR4/3 UltraScale - IP generation fails for configurations requiring more than 3 contiguous banks when targeting FGPA devices with half banks in between full banks v1.0v1.1
(Xilinx Answer 65790)DDR4/DDR3 SDRAM IP - when using a Custom Memory part some timing parameters are not updated correctlyv1.0v1.1
(Xilinx Answer 65652)DDR3/DDR4 SDRAM IP - AXI enabled designs incorrectly have data mask tied to GND during Read-Modify-Writev1.0v1.1
(Xilinx Answer 65372)DDR4/DDR3 IP - Vivado GUI Simulations fail with data errors when using VCS simulatorv1.0v1.1
(Xilinx Answer 64188)MIG UltraScale - sys_rst missing set_false_path constraintv7.0v1.1
(Xilinx Answer 62086)MIG UltraScale DDR4/DDR3 - Performance Traffic Generator only works with "ROW COLUMN BANK" Address mappingv5.0 Rev1v1.1
(Xilinx Answer 65261)MIG UltraScale DDR4/DDR3 - Dynamic DCI does not work for select devicesv7.1v1.0
(Xilinx Answer 64775)MIG UltraScale DDR3 - tZQinit violations seen during DDR3 simulationsv7.1v1.0
(Xilinx Answer 64923)MIG UltraScale - [Xicom 50-24] error message occurs after programing devicev7.0v1.0
(Xilinx Answer 64773)MIG UltraScale DDR4/DDR3 - customization GUI shows incorrect Enable Chip Select Pin option when recustomizing IPv7.0v1.0
(Xilinx Answer 63787)MIG UltraScale DDR3 - ERRORs in simulation are seen when using Micron memory model for sg125 speed grade with CAS latency = 9 and CAS Write Latency = 7v7.0v1.0
(Xilinx Answer 64071)MIG UltraScale - custom memory parts fail simulationv7.0v1.0
(Xilinx Answer 63852)MIG UltraScale DDR3 - Usage of HR banks requires user to update the output_impedance of all ports using reset_property commandv7.0N/A
(Xilinx Answer 64410)UltraScale DDR3 IP - Can either external or internal Vref be used? There is no option within the MIG tool. v7.0N/A
(Xilinx Answer 64655)DDR3 UltraScale - Dual Rank RDIMM - IP generation incorrectly enables address mirroring for dual rank DDR3 RDIMMs v7.0v7.1
(Xilinx Answer 64010)MIG UltraScale DDR4/DDR3 - memory controller may hang when in "Strict" modevv7.0v7.1
(Xilinx Answer 64146)MIG UltraScale DDR3 - simulation warnings for 16Gb and 8Gb DDR3 TwinDie partsv7.0v7.1
(Xilinx Answer 64069)MIG UltraScale - The Memory Byte/Bank Planner does not honor previously set PROHIBIT pinsv7.0v7.1
(Xilinx Answer 64063)MIG UltraScale DDR4/3 - DIMM tool tip incorrectly lists the density for the base component part v7.0v7.1
(Xilinx Answer 63789)MIG UltraScale DDR3/DDR3L (HR banks only) - It is required to target a memory device that is one speed grade faster than the target datarate when using UltraScale -2/-3 speed grades within HR banks v7.0v7.1
(Xilinx Answer 63261)MIG UltraScale DDR3/DDR4/QDRII+ - Multi-driver errors found during Lint checkv6.1v7.0
(Xilinx Answer 64431)MIG UltraScale - ]Xicom 50-38] xicom: Invalid memory type value detected from MIG core: 0.v6.1v7.0
(Xilinx Answer 63596)MIG UltraScale - HOLD violations may be seen when using 2014.4.1v6.1v7.0
(Xilinx Answer 64070)MIG UltraScale - designs with multiple controllers may generate ERROR::34 messagev6.1v7.0
(Xilinx Answer 63240)MIG UltraScale DDR4/DDR3 - PHY Only Documentation - PG150 includes incorrect usage of "rdDataEn" in relation to "per_rd_done" (periodic read operation) and "rmw_rd_done" (RMW Operation)v6.1v7.0
(Xilinx Answer 62930)MIG UltraScale DDR3/DDR4 - tCCD and tRTW violations can cause data errors in multi-rank and DDR4 x16 configurationsv6.1v7.0
(Xilinx Answer 62776)MIG UltraScale DDR3/DDR4 - ECC fault injection does not workv6.1v7.0
(Xilinx Answer 62774)MIG UltraScale - timing failures may be seen with MIG generated example designv6.1v7.0
(Xilinx Answer 62649)MIG UltraScale - GUI allows core generation even if all address and control byte lanes have not been selectedv6.0v7.0
(Xilinx Answer 59989)MIG UltraScale - Critical warnings are generated when multiple MIG instances are included in a designv5.0v7.0
(Xilinx Answer 60528)MIG UltraScale DDR3 - Vivado may fail to generate output products with 64-bit data widthv5.0v7.0
(Xilinx Answer 59991)MIG UltraScale - When running QuestaSim simulation within the Vivado GUI, the simulation is not successful. v5.0v7.0
(Xilinx Answer 59990)MIG UltraScale - IPI MIG simulation does not have memory models availablev5.0v7.0
(Xilinx Answer 61076)MIG UltraScale - Multiple instances of MIG IP fail with "[Place 30-678] Failed to do clock region partitioning"v5.0 Rev1v6.1
(Xilinx Answer 62321)MIG UltraScale DDR3/DDR4 - User Interface ports direction incorrect in instantiation templatev5.0v6.1
(Xilinx Answer 62050)MIG UltraScale DDR4/3 - Can reset_n be allocated to an I/O or does it have to be within a memory interface bank?v5.0v6.1
(Xilinx Answer 61909)MIG UltraScale DDR3/DDR4 - app_wdf_data format clarificationv6.0v6.1
(Xilinx Answer 61901)MIG UltraScale DDR3/DDR4 - memory model violations observed during simulationv5.0 Rev1N/A
(Xilinx Answer 61696)MIG UltraScale - the funcsim.v/.vhdl structural simulation model is not supportedv5.0 Rev1N/A
(Xilinx Answer 61129)MIG UltraScale DDR3 - "ERROR: tCK(avg) minimum violation"v5.0 Rev1v6.0
(Xilinx Answer 61988)MIG UltraScale DDR4/3 - Hold violations may be seen on a path clocked by riu_clkv5.0 Rev1v6.0
(Xilinx Answer 60953)MIG UltraScale - Output Products must be generated before opening the IP Example Designv5.0 Rev1v6.0
(Xilinx Answer 59948)MIG UltraScale DDR4/DDR3 - Incorrect clock connection on dbg_hub which can have a negative timing impactv5.0v 5.0 Rev1


MIG UltraScale RLDRAM3 SDRAM

The following are post-2015.1 MIG UltraScale RLDRAM3 IP patches that are recommended be installed if currently in production but are unable to upgrade the IP to 2016.1. All other users are recommended to upgrade to 2016.1:

Answer RecordTitleVersion FoundVersion Resolved
(Xilinx Answer 66689)UltraScale RLDRAM3 IP - patch update recommended for 2015.4v1.1v2.0
(Xilinx Answer 66688)UltraScale RLDRAM3 IP - patch update recommended for 2015.3v1.0v2.0
(Xilinx Answer 66035)MIG UltraScale RLDRAM3 IP - patch update recommended for 2015.2v7.1v2.0
(Xilinx Answer 66034)MIG UltraScale RLDRAM3 IP - patch update recommended for 2015.1v7.0v2.0


The following table provides known issues for MIG UltraScale RLDRAM3 SDRAM.

Note: The "Version Found" column lists the version the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer RecordTitleVersion FoundVersion Resolved
(Xilinx Answer 67967)UltraScale Memory IP - Error: [Unisim MMCME3_ADV-10] The calculated PFD frequency=799.360512 Mhz. This exceeds the permitted PFD frequency range v1.3Not Resolved
(Xilinx Answer 67957)UltraScale Memory IP - "Phy core regeneration & stitching failed" occurs when opening an older Vivado project without upgrading the Memory IPv1.3Not Resolved
(Xilinx Answer 67933)UltraScale Memory IP - Error messages generated after archiving and moving a project containing Memory IP with a custom part.v1.3Not Resolved
(Xilinx Answer 67922)RLDRAM3 IP - Example Design - Advanced Traffic Generator (ATG) detects data compare errors when testing with the TG_MAX_NUM_OF_ITER_ADDR parameter is set to a large valuev1.2 (Rev. 1)Not Resolved
(Xilinx Answer 67392)UltraScale and UltraScale+ Memory IP - pulse width violations can occurv1.2 (Rev. 1)Not Resolved
(Xilinx Answer 67164)UltraScale+ Memory IP - timing failures occur due to high congestion levelsv2.0Not Resolved
(Xilinx Answer 59990)MIG UltraScale - IPI MIG simulation does not have memory models availablev5.0Not Resolved
(Xilinx Answer 67684)UltraScale Memory IP - moving IP that uses custom memory parts (CSV) might cause problemsv1.2 (Rev. 1)v1.3
(Xilinx Answer 66951)Memory IP - WARNING: [DRC 23-20] Rule violation (PDCN-1569) LUT equation term checkv1.2v1.3
(Xilinx Answer 67367)UltraScale RLDRAM3 IP - when targeting 576Mb and 1.125Gb x36 parts an extra address bit exists on the pin outv1.2 (Rev. 1)v1.3
(Xilinx Answer 67335)UltraScale+ Memory IP - devices fail during opt_design with custom memory part if generation of the IP output products is skippedv1.2 (Rev. 1)v1.3
(Xilinx Answer 66360)UltraScale Memory IP - Core Container does not include *.csv file when a custom memory part is createdv1.0v1.3
(Xilinx Answer 67225)UltraScale Memory IP - CLOCK_DEDICATED_ROUTE BACKBONE constraint not automatically generated by IPv1.2v1.2 (Rev.1)
(Xilinx Answer 67224)UltraScale Memory IP - CLOCK_DEDICATED_ROUTE BACKBONE constraint must be applied to the CLKIN1 pin of the MMCMv1.2v1.2 (Rev. 1)
(Xilinx Answer 67125)RLDRAM3 IP - spec violation allowed for Read Latency (RL) of 15 and -107 speed binv1.2v1.2 (Rev. 1)
(Xilinx Answer 66589)RLDRAM3 IP - ERROR: [Place 30-484] The packing of lutram instances into lutram capable slices could not be obeyed.v1.1v1.2
(Xilinx Answer 66678)UltraScale Memory IP - Design fails during 'opt_design' when using Custom CSVv1.1v1.2
(Xilinx Answer 65431)UltraScale Memory IP - Designs generated pre-v1.0 with "No Buffer" clocking option require path update to CLOCK DEDICTAED ROUTE constraintv1.0v1.2
(Xilinx Answer 65371)RLDRAM3 IP - hardware failures might occur at lower frequencies of operationv1.0v1.2
(Xilinx Answer 62543)MIG UltraScale - Certain speed grades incorrectly prevent previously allowed input clock periodsv6.0v1.2
(Xilinx Answer 65787)RLDRAM3 IP - Calibration failures can occur when Data Mask (DM) is disabledv1.0v1.1
(Xilinx Answer 65651)RLDRAM3 IP - Read Latency of 17 is not a valid value for "-093E" partsv1.0v1.1
(Xilinx Answer 65219)RLDRAM3 IP - older versions of MIG UltraScale RLDRAM IP cause critical warnings in 2015.3v1.0v1.1
(Xilinx Answer 65370)Memory IP - pblocks containing UltraScale Memory IP logic must be contained within the same clock region the memory I/O is located inv1.0v1.1
(Xilinx Answer 65327)UltraScale Memory IP - CRITICAL WARNING: [Xicom 50-38] xicom: The current version of Vivado does not support this detected version of the MIG core. 2015.2 is the last version supporting it v1.0v1.1
(Xilinx Answer 64778)MIG UltraScale - When using the Auto Assign feature of Bank Planner, an error message is not issued when the memory ports do not fit into a half bankv7.0v1.1
(Xilinx Answer 64188)MIG UltraScale - sys_rst missing set_false_path constraintv7.0v1.1
(Xilinx Answer 64946)MIG UltraScale RLDRAM3 - PCB pull-down required on RESET#v7.1v1.0
(Xilinx Answer 64772)MIG UltraScale RLDRAM3 - timing failures in mmcm_clk0 domain as a result of too many logic levelsv7.1v1.0
(Xilinx Answer 64923)MIG UltraScale - [Xicom 50-24] error message occurs after programing devicev7.0v1.0
(Xilinx Answer 64486)MIG UltraScale RLDRAM3 - tWTR violations seen at frequencies greater than 750MHzv7.0v1.0
(Xilinx Answer 64071)MIG UltraScale - custom memory parts fail simulationv7.0v1.0
(Xilinx Answer 64642)MIG UltraScale RLDRAM3 - IP upgrade in 2015.1 creates DDR4 controllerv7.0v7.1
(Xilinx Answer 64069)MIG UltraScale - The Memory Byte/Bank Planner does not honor previously set PROHIBIT pinsv7.0v7.1
(Xilinx Answer 64431)MIG UltraScale - ]Xicom 50-38] xicom: Invalid memory type value detected from MIG core: 0.v6.1v7.0
(Xilinx Answer 62593)MIG UltraScale RLDRAM3 - default bank selection for 72-bit designs fails to select all data byte lanesv6.1v7.0
(Xilinx Answer 62774)MIG UltraScale - timing failures may be seen with MIG generated example designv6.1v7.0
(Xilinx Answer 63596)MIG UltraScale - HOLD violations may be seen when using 2014.4.1v6.1v7.0
(Xilinx Answer 63687)MIG UltraScale RLDRAM3 - IDELAY taps don't move during QVLD Calibration which may cause data errors in hardwarev6.1v7.0
(Xilinx Answer 64070)MIG UltraScale - designs with multiple controllers may generate ERROR::34 messagev6.1v7.0
(Xilinx Answer 63238)MIG UltraScale RLDRAM3 - timing failures in mmcm_clkout0 domainv6.1v7.0
(Xilinx Answer 62649)MIG UltraScale - GUI allows core generation even if all address and control byte lanes have not been selectedv6.0v7.0
(Xilinx Answer 59989)MIG UltraScale - Critical warnings are generated when multiple MIG instances are included in a designv5.0v7.0
(Xilinx Answer 59991)MIG UltraScale - When running QuestaSim simulation within the Vivado GUI, the simulation is not successful.v5.0v7.0
(Xilinx Answer 61076)MIG UltraScale - Multiple instances of MIG IP fail with "[Place 30-678] Failed to do clock region partitioning"v5.0 Rev1v6.1
(Xilinx Answer 61627)MIG UltraScale RLDRAM3 - data mask does not work for RLDRAM3 designsv5.0 Rev1v6.0
(Xilinx Answer 60953)MIG UltraScale - Output Products must be generated before opening the IP Example Designv5.0 Rev1v6.0
(Xilinx Answer 60951)MIG UltraScale RLDRAM3 and QDRII+ - timing failure from XiPHY to riu_clkv5.0 Rev1v6.0
(Xilinx Answer 61696)MIG UltraScale - the funcsim.v/.vhdl structural simulation model is not supported
v5.0 Rev1
N/A

MIG UltraScale QDRII+ SRAM

The following table provides known issues for MIG UltraScale QDRII+ SRAM.

Note: The "Version Found" column lists the version the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer RecordTitleVersion FoundVersion Resolved
(Xilinx Answer 67967)UltraScale Memory IP - Error: [Unisim MMCME3_ADV-10] The calculated PFD frequency=799.360512 Mhz. This exceeds the permitted PFD frequency range v1.3Not Resolved
(Xilinx Answer 67957)UltraScale Memory IP - "Phy core regeneration & stitching failed" occurs when opening an older Vivado project without upgrading the Memory IPv1.3Not Resolved
(Xilinx Answer 67933)UltraScale Memory IP - Error messages generated after archiving and moving a project containing Memory IP with a custom part.v1.3Not Resolved
(Xilinx Answer 67959)UltraScale QDRII+ IP - XSDB reports Memory Frequency incorrectlyv1.2 (Rev. 1)Not Resolved
(Xilinx Answer 67392)UltraScale and UltraScale+ Memory IP - pulse width violations can occurv1.2 (Rev. 1)Not Resolved
(Xilinx Answer 67336)UltraScale QDRII+ IP - *_ooc.xdc constraints file does not get generated in Out-Of-Context (OOC) modev1.2 (Rev. 1)Not Resolved
(Xilinx Answer 59990)MIG UltraScale - IPI MIG simulation does not have memory models availablev5.0Not Resolved
(Xilinx Answer 67684)UltraScale Memory IP - moving IP that uses custom memory parts (CSV) might cause problemsv1.2 (Rev. 1)v1.3
(Xilinx Answer 67335)UltraScale+ Memory IP - devices fail during opt_design with custom memory part if generation of the IP output products is skippedv1.2 (Rev. 1)v1.3
(Xilinx Answer 67225)UltraScale Memory IP - CLOCK_DEDICATED_ROUTE BACKBONE constraint not automatically generated by IPv1.2v1.2 (Rev. 1)
(Xilinx Answer 66951)Memory IP - WARNING: [DRC 23-20] Rule violation (PDCN-1569) LUT equation term checkv1.2v1.3
(Xilinx Answer 66360)UltraScale Memory IP - Core Container does not include *.csv file when a custom memory part is createdv1.0v1.3
(Xilinx Answer 67224)UltraScale Memory IP - CLOCK_DEDICATED_ROUTE BACKBONE constraint must be applied to the CLKIN1 pin of the MMCMv1.2v1.2 (Rev. 1)
(Xilinx Answer 66678)UltraScale Memory IP - Design fails during 'opt_design' when using Custom CSVv1.1v1.2
(Xilinx Answer 65431)UltraScale Memory IP - Designs generated pre-v1.0 with "No Buffer" clocking option require path update to CLOCK DEDICTAED ROUTE constraintv1.0v1.2
(Xilinx Answer 62543)MIG UltraScale - Certain speed grades incorrectly prevent previously allowed input clock periodsv6.0v1.2
(Xilinx Answer 65370)Memory IP - pblocks containing UltraScale Memory IP logic must be contained within the same clock region the memory I/O is located inv1.0v1.1
(Xilinx Answer 65327)UltraScale Memory IP - CRITICAL WARNING: [Xicom 50-38] xicom: The current version of Vivado does not support this detected version of the MIG core. 2015.2 is the last version supporting itv1.0v1.1
(Xilinx Answer 64778)MIG UltraScale - When using the Auto Assign feature of Bank Planner, an error message is not issued when the memory ports do not fit into a half bankv7.0v1.1
(Xilinx Answer 64188)MIG UltraScale - sys_rst missing set_false_path constraintv7.0v1.1
(Xilinx Answer 64071)MIG UltraScale - custom memory parts fail simulationv7.0v1.0
(Xilinx Answer 64923)MIG UltraScale - [Xicom 50-24] error message occurs after programing devicev7.0v1.0
(Xilinx Answer 64783)MIG UltraScale QDRII+ - XSDB Debugger indicates MicroBlaze has failed but calibration completesv7.0v1.0
(Xilinx Answer 64488)MIG UltraScale QDRII+ - core generation fails due to invalid Memory Device Interface Speed settingv7.0v7.1
(Xilinx Answer 64069)MIG UltraScale - The Memory Byte/Bank Planner does not honor previously set PROHIBIT pinsv7.0v7.1
(Xilinx Answer 64006)MIG UltraScale QDRII+ - unexpected DRC for correct placement of memory clock pair (K/K#)v7.0v7.1
(Xilinx Answer 63689)MIG UltraScale QDRII+ - Read latency 2.0 (RL2) and Burst length 2 (BL2) designs fail simulation with Cypress memory modelv7.0v7.1
(Xilinx Answer 64427)MIG UltraScale - calibration and intermittent data errors due to improper calibration resultsv6.1v7.0
(Xilinx Answer 64431)MIG UltraScale - ]Xicom 50-38] xicom: Invalid memory type value detected from MIG core: 0.v6.1v7.0
(Xilinx Answer 62774)MIG UltraScale - timing failures may be seen with MIG generated example designv6.1v7.0
(Xilinx Answer 64070)MIG UltraScale - designs with multiple controllers may generate ERROR::34 messagev6.1v7.0
(Xilinx Answer 63261)MIG UltraScale DDR3/DDR4/QDRII+ - Multi-driver errors found during Lint checkv6.1v7.0
(Xilinx Answer 62649)MIG UltraScale - GUI allows core generation even if all address and control byte lanes have not been selectedv6.0v7.0
(Xilinx Answer 59989)MIG UltraScale - Critical warnings are generated when multiple MIG instances are included in a designv5.0v7.0
(Xilinx Answer 59991)MIG UltraScale - When running QuestaSim simulation within the Vivado GUI, the simulation is not successful.v5.0v7.0
(Xilinx Answer 62157)Design Advisory for MIG UltraScale QDRII+ - pinout DRC violations not caught in I/O Plannerv5.0 Rev1v6.0
(Xilinx Answer 61696)MIG UltraScale - the funcsim.v/.vhdl structural simulation model is not supportedv5.0 Rev1N/A
(Xilinx Answer 61555)MIG UltraScale QDRII+ - multi-driver issue in Cypress model causes data error in simulationv5.0 Rev1N/A
(Xilinx Answer 61076)MIG UltraScale - Multiple instances of MIG IP fail with "[Place 30-678] Failed to do clock region partitioning"v5.0 Rev1v6.1
(Xilinx Answer 60953)MIG UltraScale - Output Products must be generated before opening the IP Example Designv5.0 Rev1v6.0
(Xilinx Answer 60951)MIG UltraScale RLDRAM3 and QDRII+ - timing failure from XiPHY to riu_clkv5.0 Rev 1v6.0
(Xilinx Answer 60047)MIG UltraScale QDRII+ - incorrect parameter values for 36-bit designs using x16 components
v5.0N/A

MIG UltraScale QDRIV SRAM

The following table provides known issues for MIG UltraScale QDRIV SRAM.

Note: The "Version Found" column lists the version the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer RecordTitleVersion FoundVersion Resolved
(Xilinx Answer 68037)UltraScale and UltraScale QDRIV IP - vio_tg_start is unconnected to Advanced Traffic Generator (ATG)v1.2Not Resolved
(Xilinx Answer 67967)UltraScale Memory IP - Error: [Unisim MMCME3_ADV-10] The calculated PFD frequency=799.360512 Mhz. This exceeds the permitted PFD frequency range v1.2Not Resolved
(Xilinx Answer 67957)UltraScale Memory IP - "Phy core regeneration & stitching failed" occurs when opening an older Vivado project without upgrading the Memory IPv1.2Not Resolved
(Xilinx Answer 67933)UltraScale Memory IP - Error messages generated after archiving and moving a project containing Memory IP with a custom part.v1.2Not Resolved
(Xilinx Answer 67392)UltraScale and UltraScale+ Memory IP - pulse width violations can occurv1.1 (Rev. 1)Not Resolved
(Xilinx Answer 59990)MIG UltraScale - IPI MIG simulation does not have memory models availablev5.0Not Resolved
(Xilinx Answer 67684)UltraScale Memory IP - moving IP that uses custom memory parts (CSV) might cause problemsv1.1 (Rev. 1)v1.2
(Xilinx Answer 67335)UltraScale+ Memory IP - devices fail during opt_design with custom memory part if generation of the IP output products is skippedv1.1 (Rev. 1)v1.2
(Xilinx Answer 67225)UltraScale Memory IP - CLOCK_DEDICATED_ROUTE BACKBONE constraint not automatically generated by IPv1.1v1.2
(Xilinx Answer 67224)UltraScale Memory IP - CLOCK_DEDICATED_ROUTE BACKBONE constraint must be applied to the CLKIN1 pin of the MMCMv1.1v1.2
(Xilinx Answer 66951)Memory IP - WARNING: [DRC 23-20] Rule violation (PDCN-1569) LUT equation term checkv1.1v1.2
(Xilinx Answer 66360)UltraScale Memory IP - Core Container does not include *.csv file when a custom memory part is createdv1.0v1.2

Revision History:
04/16/2014Initial release
06/04/2014Updated for 2014.2
10/01/2014Updated for 2014.3
10/16/2014Added link to Hardware Debug Guide
11/07/2014Updated for 2014.4
12/16/2014Added AR62930
01/08/2015Added AR63261
04/15/2015Updated for 2015.1 release
06/24/2015Updated for 2015.2 release
07/06/2015Added AR64887
07/09/2015Added 64923
08/07/2015Added 64946
09/30/2015 Updated for 2015.3
11/24/2015Updated for 2015.4
01/26/2015Added 66471
04/13/2016Updated for 2016.1 release
09/19/2016Added 67891
10/05/2016Updated for 2016.3 release

Attachments

Associated Attachments

Name File Size File Type
memory_device_support_2016_1.xlsx 23 KB XLSX

Linked Answer Records

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
59625 MIG UltraScale - Design Methodology Checklist N/A N/A
59990 MIG Ultrascale - IPI MIG simulation does not have memory models available N/A N/A
59991 MIG Ultrascale - When running QuestaSim simulation within the Vivado GUI, the simulation is not successful. N/A N/A
59989 MIG Ultrascale - Critical warnings are generated when multiple MIG instances are included in a design N/A N/A
60047 MIG UltraScale QDRII+ - incorrect parameter values for 36-bit designs using x16 components N/A N/A
60181 MIG UltraScale DDR4/DDR3 - Timing violations may occur at higher data rates N/A N/A
61076 MIG UltraScale - Mutiple instances of MIG IP fails with "[Place 30-678] Failed to do clock region partitioning" N/A N/A
61129 MIG UltraScale DDR3 - "ERROR: tCK(avg) minimum violation" N/A N/A
61627 MIG UltraScale RLDRAM3 - data mask does not work for RLDRAM3 designs N/A N/A
61304 MIG UltraScale - Clocking Guidelines and Requirements N/A N/A
61696 MIG UltraScale - the funcsim.v/.vhdl structural simulation model is not supported N/A N/A
61725 MIG UltraScale DDR4 - Micron DDR4 part name shown in MIG GUI is obsolete N/A N/A
61901 MIG UltraScale DDR3/DDR4 - memory model violations observed during simulation N/A N/A
61909 MIG UltraScale DDR3/DDR4 - app_wdf_data format clarification N/A N/A
60528 MIG UltraScale DDR3/DDR4 - Vivado may fail to generate output products with 64-bit data width N/A N/A
61555 MIG UltraScale QDRII+ - multi-driver issue in Cypress memory model causes data errors in simulation N/A N/A
61988 MIG Ultrascale DDR4/3 - Hold violations may be seen on a path clocked by riu_clk N/A N/A
62055 MIG Ultrascale DDR4/3 - MIG incorrectly allows Data Mask (DM) to be disabled for AXI designs N/A N/A
61428 MIG UltraScale DDR4/DDR3 – What is the recommended flow for creating a PHY Only design? N/A N/A
62157 Design Advisory for MIG UltraScale QDRII+ - pinout DRC violations not caught in I/O Planner N/A N/A
60305 Memory Interface UltraScale DDR4/DDR3 - Hardware Debug Guide N/A N/A
62321 MIG UltraScale DDR3/DDR4 - User Inteface ports direction incorrect in instantiation template N/A N/A
62543 MIG UltraScale - Certain speed grades incorrectly prevent previously allowed input clock periods N/A N/A
62593 MIG UltraScale RLDRAM3 - default bank selection for 72-bit designs fails to select all data byte lanes N/A N/A
62615 MIG 7 Series DDR3 (IPI Flow ONLY) - Warning message generated upon IPI Upgrade - Clocking structure for MIG has been updated N/A N/A
62086 MIG UltraScale DDR4/DDR3 - Performance Traffic Generator only works with "ROW COLUMN BANK" Address mapping N/A N/A
62649 MIG UltraScale - GUI allows core generation even if all address and control byte lanes have not been selected N/A N/A
62774 MIG UltraScale - timing failures may be seen with MIG generated example design N/A N/A
62776 MIG UltraScale DDR3/DDR4 - ECC fault injection does not work N/A N/A
62930 MIG UltraScale DDR3/DDR4 - tCCD and tRTW violations can cause data errors in multi-rank and DDR4 x16 configurations N/A N/A
62872 MIG UltraScale - Replacing XCI with synthesized/implemented netlist does not work N/A N/A
63022 MIG UltraScale DDR4/3 - Designs targeting dual rank DIMMs with address mirroring fail in hardware N/A N/A
63238 MIG UltraScale RLDRAM3 - timing failures in mmcm_clkout0 domain N/A N/A
63242 MIG UltraScale - does MIG support TDQS functionality? N/A N/A
63261 MIG UltraScale DDR3/DDR4/QDRII+ - Multi-driver errors found during LINT check N/A N/A
63667 MIG UltraScale DDR4 - VIOLATION: cmdWR seen for tCK = 833ps and speed bin = 833 when using Micron Memory Model N/A N/A
63666 MIG UltraScale DDR4 - tCK SPEC_VIOLATIONs for tCK = 833ps and speed bin = 833 when using Micron Memory Model N/A N/A
63687 MIG UltraScale RLDRAM3 - IDELAY taps do not move during QVLD Calibration which can cause data errors in hardware N/A N/A
63689 MIG UltraScale QDRII+ - Read Latency 2.0 (RL2) and Burst Length 2 (BL2) designs fail simulation with Cypress memory model N/A N/A
63786 MIG UltraScale DDR4 - SPEC_VIOLATION tWR/tRTP tWR seen for tCK = 833ps and speed bin = 833 when using Micron Memory Model N/A N/A
63787 MIG UltraScale DDR3 - ERRORs in simulation are seen when using the Micron memory model for sg125 speed grade with CAS Latency = 9 and CAS Write Latency = 7 N/A N/A
63788 MIG UltraScale DDR3 - tRRD and tFAW errors seen in behavioral simulation N/A N/A
64006 MIG UltraScale QDRII+ - unexpected DRC for correct placement of memory clock pair (K/K#) N/A N/A
64010 MIG UltraScale DDR4/DDR3 - memory controller can hang when in "Strict" mode N/A N/A
64063 MIG UltraScale DDR4/3 - DIMM tool tip incorrectly lists the density for the base component part N/A N/A
64070 MIG UltraScale - designs with multiple controllers might generate ERROR::34 message N/A N/A
64069 MIG UltraScale - The Memory Byte/Bank Planner does not honor previously set PROHIBIT pins N/A N/A
64071 MIG UltraScale - custom memory parts fail simulation N/A N/A
64146 MIG UltraScale DDR3 - simulation warnings for 16Gb and 8Gb DDR3 TwinDie parts N/A N/A
64188 MIG UltraScale - sys_rst missing set_false_path constraint N/A N/A
64342 MIG UltraScale - Vivado crashes when an imported CSV file has invalid entries for custom memory part N/A N/A
64427 MIG UltraScale QDRII+ - calibration and intermittent data errors due to improper calibration results N/A N/A
64431 MIG UltraScale - [Xicom 50-38] xicom: Invalid memory type value detected from MIG core: 0. N/A N/A
64486 MIG UltraScale RLDRAM3 - tWTR violations seen at frequencies greater than 750MHz N/A N/A
64488 MIG UltraScale QDRII+ - core generation fails due to invalid Memory Device Interface Speed setting N/A N/A
64642 MIG UltraScale RLDRAM3 - IP upgrade in 2015.1 creates DDR4 controller N/A N/A
64772 MIG UltraScale RLDRAM3 - timing failures in mmcm_clk0 domain as a result of too many logic levels N/A N/A
64773 MIG UltraScale DDR4/DDR3 - customization GUI shows incorrect Enable Chip Select Pin option when recustomizing IP N/A N/A
64774 MIG UltraScale DDR4 - SETUP/HOLD violations in the mmcm_clkout0 domain N/A N/A
64775 MIG UltraScale DDR3 - tZQinit violations seen during DDR3 simulations N/A N/A
64783 MIG UltraScale QDRII+ - XSDB Debugger indicates MicroBlaze has failed but calibration completes N/A N/A
64784 MIG UltraScale DDR4 - false DRC MIG-32# errors detected for sys_clk_p/n N/A N/A
64887 MIG UltraScale - Errors occur when implementing a 2015.1 MIG (v7.0) IP in Vivado 2015.2 - Patch available N/A N/A
64923 MIG UltraScale - Hardware Manager Xicom error messages occuring after programming device N/A N/A
65219 RLDRAM3 IP - older versions of MIG UltraScale RLDRAM IP cause critical warnings in 2015.3 N/A N/A
65261 MIG UltraScale DDR4/DDR3 - Dynamic DCI does not work for some devices N/A N/A
65279 DDR4/3 UltraScale - UNDEF error occurs upon generating output products when a dual slot, dual rank 72-bit DIMM is generated in an FPGA device containing only 3 vertical I/O banks N/A N/A
65370 Memory IP - pblocks containing UltraScale Memory IP logic must be contained within the same clock region the memory I/O is located in N/A N/A
65371 RLDRAM3 IP - hardware failures can occur at lower frequencies of operation N/A N/A
65395 QDRIV IP - "UNKNOWN STATE ERROR" messages reported during simulations when using QuestaSim N/A N/A
65351 MIG 7 series - GUI shows incorrect tested Vivado version number N/A N/A
65386 MIG 7 Series - When MEM_BITS changed in simulation model, FATAL error seen during simulation of MIG example design N/A N/A
66360 UltraScale Memory IP - Core Container does not include *.csv file when a custom memory part is created N/A N/A
66471 DDR4 IP - Incorrect Write Recovery (WR) value programmed to Mode Register 0 (MR0) N/A N/A
66554 DDR4 IP - a 300MHz reference input clock cannot be chosen for 1333MHz (750ps) output clock frequency N/A N/A
66589 RLDRAM3 IP - ERROR: [Place 30-484] The packing of lutram instances into lutram capable slices could not be obeyed. N/A N/A
66678 UltraScale Memory IP - Design fails during 'opt_design' when using Custom CSV N/A N/A
66560 DDR4/3 UltraScale - IP generation fails when custom part csv file is loaded for twin die component N/A N/A
66034 MIG UltraScale RLDRAM3 - patch update recommended for 2015.1 N/A N/A
66688 UltraScale RLDRAM3 IP - patch update recommended for 2015.3 N/A N/A
66689 UltraScale RLDRAM3 IP - patch update recommended for Vivado 2015.4 N/A N/A
66035 MIG UltraScale RLDRAM3 - patch update recommended for Vivado 2015.2 N/A N/A
66794 UltraScale DDR3 IP - Write errors may be seen in dual rank or dual slot configurations in Vivado 2015.3 or 2015.4 due to Dynamic ODT settings N/A N/A
66938 UltraScale+ DDR4 IP - Usage of six or more DDP (Dual Die Package/Twin Die) components is limited to 2133Mbps operation. This limit is not adhered to within the DDR4 Wizard. Manual adherence to this limit is required. N/A N/A
65372 DDR4/DDR3 IP - Vivado GUI Simulations fail with data errors when using VCS simulator N/A N/A
66951 Memory IP - WARNING: [DRC 23-20] Rule violation (PDCN-1569) LUT equation term check N/A N/A
67054 DDR4 IP - Extra CK/CK# clock pair generated for some RDIMMs and LRDIMMs N/A N/A
67125 RLDRAM3 IP - spec violation allowed for Read Latency (RL) of 15 and -107 speed bin N/A N/A
67164 UltraScale+ Memory IP - timing failures occur due to high congestion levels N/A N/A
67224 UltraScale Memory IP - CLOCK_DEDICATED_ROUTE BACKBONE constraint must be applied to the CLKIN1 pin of the MMCM N/A N/A
67225 UltraScale Memory IP - CLOCK_DEDICATED_ROUTE BACKBONE constraint not automatically generated by IP N/A N/A
67230 UltraScale DDR4 SDRAM IP - tREFI interval is incorrectly set N/A N/A
67255 UltraScale and UltraScale+ DDR4 SDRAM IP - [Place 30-487] error may occur for some configurations N/A N/A
67891 DDR4/DDR3 IP - Ping-Pong PHY behavioral simulations fail with data errors when using BFM simulation mode N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
62603 Virtex UltraScale FPGA VCU108 Evaluation Kit - Known Issues and Release Notes Master Answer Record N/A N/A
AR# 58435
Date Created 11/18/2013
Last Updated 11/07/2016
Status Active
Type Release Notes
Devices
  • Virtex UltraScale
  • Kintex UltraScale
IP
  • MIG UltraScale