In a Spartan-6 design in which the DDR_ALIGNMENT parameter of ODDR2 instance is set to C0/C1, the OFFSET OUT constraint only analyzes the timing path associated with C0/C1 but no path with C1/C0 is getting analyzed.
When DDR_ALIGNMENT = NONE, then paths with both clock pins are analyzed as expected.
Example constraints in question:
1. When local inverter on C0/C1 is used:
TIMEGRP "dataout0" OFFSET = OUT 8 ns after clk0 RISING;
TIMEGRP "dataout0" OFFSET = OUT 8 ns after clk0 FALLING;
2. When C0/C1 is inverted before going to ODDR2 (using BUFIO2 or PLL/DCM):
TIMEGRP "dataout1" OFFSET = OUT 8 ns after clk1 TIMEGRP "clk1_c0_grp";
TIMEGRP "dataout1" OFFSET = OUT 13 ns after clk1 TIMEGRP "clk1_c1_grp";
Why does only one clock pin produce OFFSET OUT timing path when DDR_ALIGNMENT = C0/C1?
This is expected behavior.
When DDR_ALIGNMENT = C0, output paths are only captured by C0 and when DDR_ALIGNMENT = C1, output paths are only captured by C1.
With the option set to NONE, the ODDR internal configuration is as follow:
You can see the input data (D0 & D1) must be out of phase and aligned with the corresponding clock.
D0 is captured with C0 and D1 is captured with C1, which are complementary signals.
So both C0 and C1 are associated with OFFSET OUT timing paths.
For the C0/C1 situation, when the input data is aligned only with one of the 2 clocks, either C0 or C1,
Both D0 and D1 are captured in the ODDR2 with C0 (diagram above).
The internal delay FF which aligns the output data to be a DDR value breaks the D1 -> Q path.
Therefore, only one valid OFFSET OUT path exists in this configuration, which is D0 -> Q clocked by C0.
And the other way around, when C1 is selected.
For more information regarding ODDR2 configuration, please refer to UG381.