It is possible to use the same clocking module between two Virtex-7 FPGA Gen3 Integrated Block for PCI Express cores. The clocking module provides two output clocks (CLK_PCLK and CLK_PCLK_SLAVE) that can switch between 125 MHz and 250 MHz depending on the select lines.
To share the clocking module, make the connection as described below:
All output clocks of "pcie3_7x_0_pipe_clock.v", except the CLK_PCLK, are shared between both PCIe cores.
There are other limitations when sharing the clocking module between two PCIe cores. Please refer to 'Shared Clocking' section in the product guide (PG023).
12/10/2013 - Initial release