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AR# 58743

Virtex-7 FPGA Gen3 Integrated Block for PCI Express v2.2 - How can I share the same clocking module between two PCIe cores?

Description

The core configuration GUI has an option to select "Include Shared Logic (Clocking) in Example Design". It is not clear in the document how the same clocking module (*_pipe_clock.v) can be shared between two Virtex-7 FPGA Gen3 Integrated Block for PCI Express cores. There is CLK_PCLK output from the clocking module which switches between 125 MHz and 250 MHz depending on at what speed the core is working at. How does it work if the two cores are working at different speeds?

Solution

It is possible to use the same clocking module between two Virtex-7 FPGA Gen3 Integrated Block for PCI Express cores. The clocking module provides two output clocks (CLK_PCLK and CLK_PCLK_SLAVE) that can switch between 125 MHz and 250 MHz depending on the select lines.

To share the clocking module, make the connection as described below:

All output clocks of "pcie3_7x_0_pipe_clock.v", except the CLK_PCLK, are shared between both PCIe cores.

  • Connect CLK_PCLK to "pipe_pclk_in" of PCIe Core #0
  • Connect CLK_PCLK_SEL to "pipe_pclk_sel_out" of PCIe Core #0
  • Connect CLK_PCLK_SLAVE to "pipe_pclk_in" of PCIe Core #1
  • Connect CLK_PCLK_SEL_SLAVE to "pipe_pclk_sel_out" of PCIe Core #1

There are other limitations when sharing the clocking module between two PCIe cores. Please refer to 'Shared Clocking' section in the product guide (PG023).
 
Revision History
12/10/2013 - Initial release

AR# 58743
Date Created 12/10/2013
Last Updated 12/10/2013
Status Active
Type General Article
IP
  • Virtex-7 FPGA Gen3 Integrated Block for PCI Express (PCIe)