The three clock relationships originated from SDC have different impacts on SI crosstalk analysis.
From an FPGA timing analysis perspective, the impact would be the same.
To more accurately specify the clock relationships, it would be good to understand the different clock interactions.
When there are valid timing paths between two clock groups but the two clocks do not have any frequency or phase relationship and these timing paths need not to be timed, use -asynchronous.
When there are false timing paths (physically or logically non-existent) between two clock groups, use -physical_exclusive or -logical_exclusive
-logical_exclusive is used for two clocks that are defined on different source roots.
Logically exclusive clocks do not have any functional paths between them, but
might have coupling interactions with each other.
An example of logically
exclusive clocks is multiple clocks, which are selected by a MUX but can still
interact through coupling upstream of the MUX cell.
When there are physically existing but logically false paths between the two clocks, use "set_clock_groups -logical_exclusive".
-physical_exclusive is used for two clocks that are defined on the same source root by "create_clock -add".
Timing paths between these two clocks do not physically exist.
As a result you will need to use "set_clock_groups -physical_exclusive" to set them as false paths.
There is an example of "set_clock_groups" under the Section "Constraining Exclusive Clock Groups" in (UG949).
Please refer to this example which will help you understand the difference between -logical_exclusive and -physical_exclusive.